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21. 发明授权

US10784200B2 Ionizing radiation blocking in IC chip to reduce soft errors 有权
公开(公告)号：US10784200B2
公开(公告)日：2020-09-22
申请号：US13409643
申请日：2012-03-01
申请人： Mukta G. Farooq , Ian D. Melville , Kevin S. Petrarca , Kenneth P. Rodbell
发明人： Mukta G. Farooq , Ian D. Melville , Kevin S. Petrarca , Kenneth P. Rodbell
IPC分类号： H01L23/532 , H01L23/556
摘要： Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.

22. 发明授权

US08691691B2 TSV pillar as an interconnecting structure 有权
标题翻译： TSV柱作为互连结构
公开(公告)号：US08691691B2
公开(公告)日：2014-04-08
申请号：US13194214
申请日：2011-07-29
申请人： Mukta G. Farooq , Troy L. Graves-Abe , William F. Landers , Kevin S. Petrarca , Richard P. Volant
发明人： Mukta G. Farooq , Troy L. Graves-Abe , William F. Landers , Kevin S. Petrarca , Richard P. Volant
IPC分类号： H01L21/44 , H01L21/311
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2224/10126 , H01L2224/11009 , H01L2224/1145 , H01L2224/11452 , H01L2224/11602 , H01L2224/11612 , H01L2224/11614 , H01L2224/11616 , H01L2224/13009 , H01L2224/13017 , H01L2224/13022 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13147 , H01L2224/13565 , H01L2224/13583 , H01L2224/13584 , H01L2224/13647 , H01L2224/13655 , H01L2224/13679 , H01L2224/1368 , H01L2224/13681 , H01L2224/13683 , H01L2224/13684 , H01L2224/13687 , H01L2224/16147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/32225 , H01L2224/73203 , H01L2224/81191 , H01L2224/81801 , H01L2224/8385 , H01L2224/9202 , H01L2224/92143 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2924/351 , H01L2924/3512 , H01L2924/00014 , H01L2924/04953 , H01L2924/0496 , H01L2924/01074 , H01L2924/04941 , H01L2924/053 , H01L2924/014 , H01L2924/00012 , H01L2224/11 , H01L2924/00
摘要： The present invention includes embodiments of a processing method, and resulting structure, for building a chip having a TSV pillar which can be used as an interconnecting structure. The process includes the deposition of a dual diffusion barrier between the TSV and the substrate the TSV is embedded within. The TSV is then exposed from the back side of the substrate so that at least a portion of the TSV protrudes from the substrate and can be used as a contact for connecting the chip to another surface. The resulting TSV is rigid, highly conductive, can be placed in a tightly pitched grid of contacts, and reduces effects of CTE mismatch.
摘要翻译：本发明包括用于构建具有可用作互连结构的TSV柱的芯片的处理方法和结果的结构的实施例。该过程包括在TSV和衬底之间沉积TSV和衬底之间的双重扩散阻挡层。 TSV然后从衬底的背面露出，使得TSV的至少一部分从衬底突出，并且可以用作用于将芯片连接到另一表面的接触件。所产生的TSV是刚性的，高导电性的，可以放置在紧密连接的接触网格中，并减少CTE失配的影响。

23. 发明授权

US08614115B2 Photovoltaic solar cell device manufacture 失效
标题翻译：光伏太阳能电池器件制造
公开(公告)号：US08614115B2
公开(公告)日：2013-12-24
申请号：US12916236
申请日：2010-10-29
申请人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Klaus Krause , Kevin S. Petrarca , Gerd Pfeiffer , Kevin M. Prettyman , Carl Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Klaus Krause , Kevin S. Petrarca , Gerd Pfeiffer , Kevin M. Prettyman , Carl Radens , Brian C. Sapp
IPC分类号： H01L21/00 , H01L31/18
CPC分类号： H01L31/022425 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A method for manufacturing a photovoltaic solar cell device includes the following. A p-n junction having a first doping density is formed. Formation of the p-n junction is enhanced by introducing a second doping density to form high doped areas for a dual emitter application. The high doped areas are defined by a masking process integrated with the formation of the p-n junction, resulting in a mask pattern of the high doped areas. A metallization of the high doped areas occurs in accordance with the mask pattern of the high doped areas.
摘要翻译：光伏太阳能电池器件的制造方法包括以下。形成具有第一掺杂密度的p-n结。通过引入第二掺杂密度以形成用于双发射器应用的高掺杂区域来增强p-n结的形成。高掺杂区域由与p-n结的形成集成的掩模工艺限定，产生高掺杂区域的掩模图案。根据高掺杂区域的掩模图案发生高掺杂区域的金属化。

24. 发明授权

US08535970B2 Manufacturing process for making photovoltaic solar cells 失效
标题翻译：制造光伏太阳能电池的制造工艺
公开(公告)号：US08535970B2
公开(公告)日：2013-09-17
申请号：US13154140
申请日：2011-06-06
申请人： Ranier Krauser , Lawrence A. Clevenger , Kevin Prettyman , Brian Christopher Sapp , Kevin S. Petrarca , Harold John Hovel , Gerd Pfeiffer , Zhengwen Li , Carl John Radens
发明人： Ranier Krauser , Lawrence A. Clevenger , Kevin Prettyman , Brian Christopher Sapp , Kevin S. Petrarca , Harold John Hovel , Gerd Pfeiffer , Zhengwen Li , Carl John Radens
IPC分类号： H01L21/00
CPC分类号： H01L31/1804 , H01L31/02167 , H01L31/022425 , H01L31/068 , Y02E10/547 , Y02P70/521
摘要： The invention relates to a manufacturing process of a photovoltaic solar cell (100) comprising: providing high doped areas (20) on the rear side (18) of the photovoltaic solar cell (100), providing localized metal contacts (30) localized on said high doped areas (20), providing a passivation layer (50) covering a surface (52) between said contacts (30), wherein the contacts (30) remain substantially free of the passivation layer (50), and depositing a metal layer (32) for a back surface field.
摘要翻译：本发明涉及一种光伏太阳能电池（100）的制造方法，包括：在光伏太阳能电池（100）的后侧（18）上提供高掺杂区域（20），提供位于所述光伏太阳能电池（100）上的局部金属触点（30）提供覆盖所述触头（30）之间的表面（52）的钝化层（50），其中触点（30）保持基本上不含钝化层（50），并沉积金属层（50） 32）用于背面场。

25. 发明授权

US08445374B2 Soft error rate mitigation by interconnect structure 有权
标题翻译：通过互连结构缓解软错误率
公开(公告)号：US08445374B2
公开(公告)日：2013-05-21
申请号：US13361057
申请日：2012-01-30
申请人： Mukta G. Farooq , Ian D. Melville , Kevin S. Petrarca
发明人： Mukta G. Farooq , Ian D. Melville , Kevin S. Petrarca
IPC分类号： H01L21/44
CPC分类号： H01L24/16 , H01L24/11 , H01L24/13 , H01L24/81 , H01L2224/05001 , H01L2224/05023 , H01L2224/05568 , H01L2224/10126 , H01L2224/1147 , H01L2224/1148 , H01L2224/1191 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/81801 , H01L2924/00013 , H01L2924/01005 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/15787 , H01L2224/29099 , H01L2924/00 , H01L2224/05541 , H01L2224/05005
摘要： A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.
摘要翻译：一种方法产生一种结构，其包括通过柱和开口连接到集成电路芯片的载体。因此，在这种结构中，至少一个导电柱与集成电路芯片的表面延伸一段距离或高度，并且阻挡层围绕导电柱的下部，使得阻挡层覆盖柱的高度的至少一部分最接近芯片表面。载体中至少有一个开口足够大以容纳导电柱和屏障，并且导电柱和屏障位于开口中。在开口的底部使用焊料将导电柱连接到开口的底部。屏障防止焊料接触由屏障保护的导电柱的部分。

26. 发明申请

US20130122702A1 INTEGRATED VOID FILL FOR THROUGH SILICON VIA 有权
标题翻译：通过硅的集成无孔填充
公开(公告)号：US20130122702A1
公开(公告)日：2013-05-16
申请号：US13555418
申请日：2012-07-23
申请人： Richard P. Volant , Mukta G. Farooq , Kevin S. Petrarca
发明人： Richard P. Volant , Mukta G. Farooq , Kevin S. Petrarca
IPC分类号： H01L21/768
CPC分类号： H01L21/76879 , H01L21/76805 , H01L21/76898 , H01L23/481 , H01L24/16 , H01L24/29 , H01L24/82 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/29 , H01L2224/29298 , H01L2224/9202 , H01L2224/92144 , H01L2225/06541 , H01L2225/06575 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/12042 , H01L2924/14 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929 , H01L2224/05552 , H01L2924/00
摘要： A microelectronic assembly and related method of forming a through hole extending through a first chip and a second chip are provided. The first and second chip have confronting faces, metallic features join the first and second chips leaving a gap chips . A first etch creates a hole through the first chip. The hole has a first wall extending in a vertical direction, and a second wall sloping inwardly from the first wall to an inner opening to expose the gap. Material of the first or second chips exposed within the hole is sputtered to form a wall in the gap. A second etch extends the hole into the second chip. An electrically conductive through silicon via can then be formed extending through the first chip, the wall between the chips and into the second chip.
摘要翻译：提供了形成贯穿第一芯片和第二芯片的通孔的微电子组件和相关方法。第一和第二芯片具有面对面，金属特征连接第一和第二芯片留下间隙芯片。第一蚀刻通过第一芯片产生孔。孔具有沿垂直方向延伸的第一壁和从第一壁向内倾斜到内部开口的第二壁，以露出间隙。暴露在孔内的第一或第二芯片的材料被溅射以在间隙中形成壁。第二蚀刻将孔延伸到第二芯片中。然后可以形成延伸穿过第一芯片，芯片之间的壁并进入第二芯片的导电硅通孔。

27. 发明申请

US20130026606A1 TSV PILLAR AS AN INTERCONNECTING STRUCTURE 有权
标题翻译： TSV柱作为互连结构
公开(公告)号：US20130026606A1
公开(公告)日：2013-01-31
申请号：US13194214
申请日：2011-07-29
申请人： Mukta G. Farooq , Troy L. Graves-Abe , William F. Landers , Kevin S. Petrarca , Richard P. Volant
发明人： Mukta G. Farooq , Troy L. Graves-Abe , William F. Landers , Kevin S. Petrarca , Richard P. Volant
IPC分类号： H01L23/522 , H01L21/98 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2224/10126 , H01L2224/11009 , H01L2224/1145 , H01L2224/11452 , H01L2224/11602 , H01L2224/11612 , H01L2224/11614 , H01L2224/11616 , H01L2224/13009 , H01L2224/13017 , H01L2224/13022 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13147 , H01L2224/13565 , H01L2224/13583 , H01L2224/13584 , H01L2224/13647 , H01L2224/13655 , H01L2224/13679 , H01L2224/1368 , H01L2224/13681 , H01L2224/13683 , H01L2224/13684 , H01L2224/13687 , H01L2224/16147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/32225 , H01L2224/73203 , H01L2224/81191 , H01L2224/81801 , H01L2224/8385 , H01L2224/9202 , H01L2224/92143 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2924/351 , H01L2924/3512 , H01L2924/00014 , H01L2924/04953 , H01L2924/0496 , H01L2924/01074 , H01L2924/04941 , H01L2924/053 , H01L2924/014 , H01L2924/00012 , H01L2224/11 , H01L2924/00
摘要： The present invention includes embodiments of a processing method, and resulting structure, for building a chip having a TSV pillar which can be used as an interconnecting structure. The process includes the deposition of a dual diffusion barrier between the TSV and the substrate the TSV is embedded within. The TSV is then exposed from the back side of the substrate so that at least a portion of the TSV protrudes from the substrate and can be used as a contact for connecting the chip to another surface. The resulting TSV is rigid, highly conductive, can be placed in a tightly pitched grid of contacts, and reduces effects of CTE mismatch.
摘要翻译：本发明包括用于构建具有可用作互连结构的TSV柱的芯片的处理方法和结果的结构的实施例。该过程包括在TSV和衬底之间沉积TSV和衬底之间的双重扩散阻挡层。 TSV然后从衬底的背面露出，使得TSV的至少一部分从衬底突出，并且可以用作用于将芯片连接到另一表面的接触件。所产生的TSV是刚性的，高导电性的，可以放置在紧密连接的接触网格中，并减少CTE失配的影响。

28. 发明授权

US08349729B2 Hybrid bonding interface for 3-dimensional chip integration 有权
标题翻译：混合键合界面，用于三维芯片集成
公开(公告)号：US08349729B2
公开(公告)日：2013-01-08
申请号：US13418716
申请日：2012-03-13
申请人： Karl W. Barth , Ricardo A. Donaton , Spyridon Galis , Kevin S. Petrarca , Shahab Siddiqui
发明人： Karl W. Barth , Ricardo A. Donaton , Spyridon Galis , Kevin S. Petrarca , Shahab Siddiqui
IPC分类号： H01L21/4763
CPC分类号： H01L23/5389 , H01L21/76898 , H01L24/80 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/9202 , H01L2924/12044
摘要： Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.
摘要翻译：第一基板和第二基板中的每一个包括具有耐扩散电介质材料如氮化硅的表面。凹陷区域形成在耐扩散电介质材料中，并且填充有可粘结介电材料。第一和第二基板中的金属焊盘和可接合的介质材料部分的图案可以具有镜面对称性。第一和第二基板通过金属焊盘和可接合的介电材料部分之间的触点之间的触点进行物理接触和接合。通过基底通孔（TSV）结构通过键合介电材料部分形成。位于TSV结构周围的每对键合的电介质材料部分之间的界面由两个扩散电阻的介电材料层封装，使得接合界面处的金属的扩散被包含在每对键合介电材料部分内。

29. 发明申请

US20120304138A1 CIRCUIT DESIGN CHECKING FOR THREE DIMENSIONAL CHIP TECHNOLOGY 有权
标题翻译：电路设计检查三维芯片技术
公开(公告)号：US20120304138A1
公开(公告)日：2012-11-29
申请号：US13113421
申请日：2011-05-23
申请人： Mukta G. Farooq , John A. Griesemer , William Francis Landers , Kevin S. Petrarca , Richard Paul Volant
发明人： Mukta G. Farooq , John A. Griesemer , William Francis Landers , Kevin S. Petrarca , Richard Paul Volant
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one or more design layers from the mirrored side of a 3D design and merging those design layers with unmirrored design layers from the unmirrored side of a 3D design. The converted circuit design can be processed by standard verification checks. The tool may also receive design layers corresponding to an integrated circuit that will pass through multiple semiconductor chips. Each design cell is examined to determine if it corresponds to a mirrored or unmirrored side of its respective semiconductor chip. If the respective design cell corresponds to the mirrored side, the design cell is mirrored. All mirrored cells are then merged with the unmirrored design cells in the correct order. The merged design is processed by standard verification checks. The tool also has the capability to create terminal metal abstracts for two adjoining chips. One of the abstracts is mirrored and then merged with the other for connectivity and alignment checking.
摘要翻译：一种允许在3D设计层镜像之后检查三维芯片电路设计的工具。通过从3D设计的镜像侧镜像一个或多个设计层，将3D芯片设计转换为相应的2D芯片设计，并将这些设计层与未设计的设计层从3D设计的非镜面合并。转换电路设计可以通过标准验证检查进行处理。该工具还可以接收对应于将通过多个半导体芯片的集成电路的设计层。检查每个设计单元以确定它是否对应于其相应的半导体芯片的镜像或非镜像侧。如果相应的设计单元对应于镜像侧，则设计单元被镜像。然后所有镜像单元格以正确的顺序与未设计的设计单元合并。合并设计通过标准验证检查进行处理。该工具还可以为两个相邻的芯片创建终端金属摘要。其中一个摘要被镜像，然后与另一个摘要进行连接和对齐检查。

30. 发明授权

US08242604B2 Coaxial through-silicon via 有权
标题翻译：同轴穿硅通孔
公开(公告)号：US08242604B2
公开(公告)日：2012-08-14
申请号：US12607098
申请日：2009-10-28
申请人： Richard P. Volant , Mukta G. Farooq , Paul F. Findeis , Kevin S. Petrarca
发明人： Richard P. Volant , Mukta G. Farooq , Paul F. Findeis , Kevin S. Petrarca
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate. The TSV structure is provided with two or more independent electrical conductors insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage. A method of fabricating such a TSV structure is also described.
摘要翻译：硅通孔（TSV）结构在硅衬底内形成独特的同轴或三轴互连。 TSV结构设置有两个或更多个与另一个绝缘的独立电导体和与衬底绝缘的独立电导体。电导体可以连接到不同的电压或接地，使得可以将TSV结构作为同轴或三轴装置进行操作。使用各种绝缘材料的多层可用作绝缘体，其中根据介电性能，填充性能，界面粘合性，CTE匹配等来选择层。 TSV结构克服了外绝缘层中可能导致泄漏的缺陷。还描述了制造这种TSV结构的方法。

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