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21. 发明授权

US07189954B2 Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers 有权
公开(公告)号：US07189954B2
公开(公告)日：2007-03-13
申请号：US10894262
申请日：2004-07-19
申请人： Warren M. Farnworth , Sidney B. Rigg , William Mark Hiatt , Alan G. Wood , Peter A. Benson , James M. Wark , David R. Hembree , Kyle K. Kirby , Charles M. Watkins , Salman Akram
发明人： Warren M. Farnworth , Sidney B. Rigg , William Mark Hiatt , Alan G. Wood , Peter A. Benson , James M. Wark , David R. Hembree , Kyle K. Kirby , Charles M. Watkins , Salman Akram
IPC分类号： H01L31/0232 , H01L27/00
CPC分类号： H01L27/00 , B33Y80/00 , H01L27/14618 , H01L27/14625 , H01L27/14683 , H01L27/14687 , H01L2224/48091 , H01L2224/48227 , H01L2924/01077 , H01L2924/01078 , H01L2924/00014
摘要： Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.

22. 发明授权

US07155300B2 Method for using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as repairs, to select procedures the IC's will undergo, such as additional repairs 有权
公开(公告)号：US07155300B2
公开(公告)日：2006-12-26
申请号：US10401209
申请日：2003-03-27
申请人： Salman Akram , Warren M. Farnworth , Derek J. Gochnour , David R. Hembree , Michael E. Hess , John O. Jacobson , James M. Wark , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Derek J. Gochnour , David R. Hembree , Michael E. Hess , John O. Jacobson , James M. Wark , Alan G. Wood
IPC分类号： G06F19/00
CPC分类号： G06F11/006 , H01L2223/5444
摘要： An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the IC's. The ID codes of the IC's are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the IC's is then accessed, and additional repair procedures the IC's may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.

23. 发明授权

US06544461B1 Test carrier with molded interconnect for testing semiconductor components 失效
标题翻译：带有模拟互连的测试载体，用于测试半导体元件
公开(公告)号：US06544461B1
公开(公告)日：2003-04-08
申请号：US09677555
申请日：2000-10-02
申请人： David R. Hembree , Salman Akram , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , John O. Jacobson , James M. Wark , Syed Sajid Ahmad
发明人： David R. Hembree , Salman Akram , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , John O. Jacobson , James M. Wark , Syed Sajid Ahmad
IPC分类号： B29C4502
CPC分类号： G01R1/0483
摘要： A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects. A gasket may be used to protect the interconnect contacts during the molding step.
摘要翻译：提供了用于测试半导体部件的半导体载体，例如裸芯片和芯片级封装，以及制造载体的方法。载体包括模制塑料基底，引线框架和互连件。互连件包括用于与组件上的相应触点（例如，接合焊盘，焊球）进行临时电连接的触点。通过将互连件附接到引线框架，然后将塑料基底模制到互连和引线框架来制造载体。替代实施例的载体包括多个互连件模制或层压的板。另外，夹子构件保持电路板上与组件电连通的组件。可以在模制步骤期间使用垫圈来保护互连触点。

24. 发明授权

US06419143B2 Utilize ultrasonic energy to reduce the initial contact forces in known-good-die or permanent contact systems 有权
公开(公告)号：US06419143B2
公开(公告)日：2002-07-16
申请号：US09921621
申请日：2001-08-03
申请人： David R. Hembree , Michael E. Hess , John O. Jacobson , Warren M. Farnworth , Alan G. Wood
发明人： David R. Hembree , Michael E. Hess , John O. Jacobson , Warren M. Farnworth , Alan G. Wood
IPC分类号： B23K2010
CPC分类号： B23K20/10 , B23K2101/38
摘要： A machine and method for bonding puncture-type conductive contact members of an interconnect to the bond pads of a bare semiconductor die includes the use of one or two ultrasonic vibrators mounted to vibrate one or both of the die and interconnect. A short axial linear burst of ultrasonic energy enables the contact members to pierce hard oxide layers on the surfaces of the bond pads at a much lower compressive force and rapidly achieve full penetration depth.

25. 发明授权

US06210984B1 Method and apparatus for automatically positioning electronic dice within component packages 有权
标题翻译：电子管芯在组件封装内自动定位的方法和装置
公开(公告)号：US06210984B1
公开(公告)日：2001-04-03
申请号：US09399640
申请日：1999-09-20
申请人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
发明人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
IPC分类号： H01L2166
CPC分类号： H01L21/67276 , G01R31/2851 , G01R31/2886 , G01R31/2893 , G01R31/311 , H01L21/67126 , H01L21/67242 , H01L21/67259 , H01L21/681 , H01L24/74 , H01L2924/12042 , H01L2924/14 , H05K13/08 , Y10T29/49004 , Y10T29/49131 , Y10T29/53174 , Y10T29/53178 , H01L2924/00
摘要： A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the dice with the temporary test package bases, and an automated robot arm system is employed to retrieve and assemble the dice with the various package components. The invention has particular utility in the burn-in and other pre-packaging testing of dice to establish known good dice (KGD).
摘要翻译：从临时测试包的组件组装和拆卸要测试的半导体骰子的方法和装置。采用计算机控制的视觉系统将骰子与临时测试包基座对准，并且采用自动机器人手臂系统来检索和组装骰子与各种包装部件。本发明在骰子的老化和其他预包装测试中具有特殊的用途，以建立已知的骰子（KGD）。

26. 发明授权

US6045026A Utilize ultrasonic energy to reduce the initial contact forces in known-good-die or permanent contact systems 失效
公开(公告)号：US6045026A
公开(公告)日：2000-04-04
申请号：US27690
申请日：1998-02-23
申请人： David R. Hembree , Michael E. Hess , John O. Jacobson , Warren M. Farnworth , Alan G. Wood
发明人： David R. Hembree , Michael E. Hess , John O. Jacobson , Warren M. Farnworth , Alan G. Wood
IPC分类号： B23K20/10
CPC分类号： B23K20/10 , B23K2201/38
摘要： A machine and method for bonding puncture-type conductive contact members of an interconnect to the bond pads of a bare semiconductor die includes the use of one or two ultrasonic vibrators mounted to vibrate one or both of the die and interconnect. A short axial linear burst of ultrasonic energy enables the contact members to pierce hard oxide layers on the surfaces of the bond pads at a much lower compressive force and rapidly achieve full penetration depth.

27. 发明授权

US6040702A Carrier and system for testing bumped semiconductor components 失效
标题翻译：用于测试碰撞半导体元件的载体和系统
公开(公告)号：US6040702A
公开(公告)日：2000-03-21
申请号：US888075
申请日：1997-07-03
申请人： David R. Hembree , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , Salman Akram
发明人： David R. Hembree , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , Salman Akram
IPC分类号： G01R31/26 , G01R1/04 , G01R1/073 , G01R31/02 , H01L21/66 , H01L23/12 , H01L23/32 , H01R13/631 , H01R13/642 , H01R33/76
CPC分类号： G01R1/0483 , H01L2224/0401 , H01L2224/05552 , H01L2224/81385 , H01L2924/01021 , H01L2924/01087 , H01L2924/09701
摘要： A semiconductor carrier and system for testing bumped semiconductor components, such as dice and packages, having contact bumps are provided. The carrier includes a base, an interconnect, and a force applying mechanism. The interconnect includes patterns of contact members adapted to electrically contact the contact bumps. The interconnect can include a substrate having contact members formed as recesses, or as projections, covered with conductive layers. Alternately, the interconnect can be a multi layered tape bonded directly to a base of the carrier. In addition to providing electrical connections, the contact members perform an alignment function by self centering the contact bumps within the contact members. The carrier can also include an alignment member configured to align the components with the interconnect. The system can include the carrier, a socket, and a testing apparatus such as a burn-in board in electrical communication with test circuitry.
摘要翻译：提供了一种半导体载体和系统，用于测试具有接触凸块的凸起的半导体部件，例如芯片和封装。载体包括基底，互连和力施加机构。互连包括适于电接触接触凸块的接触构件的图案。互连可以包括具有形成为凹陷的接触构件的衬底，或者作为突出部的覆盖有导电层的衬底。或者，互连可以是直接结合到载体的基底的多层带。除了提供电连接之外，接触构件通过使接触构件内的接触凸块自对中来执行对准功能。载体还可以包括配置成将部件与互连对准的对准部件。该系统可以包括载体，插座和诸如与测试电路电连接的老化板的测试装置。

28. 发明授权

US6016060A Method, apparatus and system for testing bumped semiconductor components 失效
公开(公告)号：US6016060A
公开(公告)日：2000-01-18
申请号：US823490
申请日：1997-03-25
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood , David R. Hembree
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood , David R. Hembree
IPC分类号： G01R1/04 , G01R1/067 , G01R1/073 , G01R31/28 , G01R31/26
CPC分类号： G01R1/0466
摘要： A method, apparatus and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The apparatus includes an interconnect having patterns of contact members adapted to electrically contact the contact bumps. Each contact member includes an array of one or more electrically conductive projections in electrical communication with an associated conductor. The projections form contact members for retaining individual contact bumps on the semiconductor components. The projections can be pillars having angled faces covered with a conductive layer. Alternately the projections can be a material deposited on the substrate, or can be microbumps formed on multi layered tape bonded to the substrate. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.

29. 发明授权

US5952840A Apparatus for testing semiconductor wafers 失效
公开(公告)号：US5952840A
公开(公告)日：1999-09-14
申请号：US770942
申请日：1996-12-31
申请人： Warren M. Farnworth , Salman Akram , Alan G. Wood , David R. Hembree , James M. Wark , John O. Jacobson
发明人： Warren M. Farnworth , Salman Akram , Alan G. Wood , David R. Hembree , James M. Wark , John O. Jacobson
IPC分类号： G01R1/04 , G01R31/28 , G01R31/02
CPC分类号： G01R1/0491 , G01R31/2886
摘要： A method, apparatus and system for testing semiconductor wafers are provided. The method includes providing a wafer carrier to provide an electrical path for receiving and transmitting test signals to the wafer. The wafer carrier includes a base for retaining the wafer, and an interconnect having contact members configured to establish electrical communication with contact locations on the wafer. The wafer carrier can include one or more compressible spring members configured to bias the wafer and interconnect together in the assembled carrier. The wafer carrier can be assembled, with the wafer in alignment with the interconnect, using optical alignment techniques, and an assembly tool similar to aligner bonder tools used for flip chip bonding semiconductor dice. A system for use with the carrier can include a testing apparatus configured to apply test signals through the carrier to the wafer while the wafer is subjected to temperature cycling.

30. 发明授权

US5929647A Method and apparatus for testing semiconductor dice 失效
标题翻译：测试半导体骰子的方法和装置
公开(公告)号：US5929647A
公开(公告)日：1999-07-27
申请号：US674473
申请日：1996-07-02
申请人： Salman Akram , Alan G. Wood , David R. Hembree , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , David R. Hembree , Warren M. Farnworth
IPC分类号： G01R1/04 , G01R31/28 , G01R1/073 , G01R31/02
CPC分类号： G01R31/2886 , G01R1/0483 , H01L2224/05553 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/15151 , H01L2924/30107
摘要： A method and carrier for testing semiconductor dice such as bare dice or chip scale packages are provided. The carrier includes a base for retaining a single die, an interconnect for establishing temporary electrical communication with the die, and a force applying mechanism for biasing the die and interconnect together. In an illustrative embodiment the base includes conductors arranged in a universal pattern adapted to electrically connect to different sized interconnects. Interconnects are thus interchangeable on a base for testing different types of dice using the same base. The conductors on the base can be formed on a planar active surface of the base or on a stepped active surface having different sized cavities for mounting different sized interconnects. In an alternate embodiment the carrier includes an interposer. In a first interposer embodiment, the interposer connects directly to external test circuitry and can be changed to accommodate different sized interconnects. In a second interposer embodiment, the interposer connects to conductors on the base and adapts the base for use with different sized interconnects.
摘要翻译：提供了用于测试半导体裸片（例如裸裸片或芯片级封装）的方法和载体。载体包括用于保持单个管芯的基座，用于建立与管芯的临时电连通的互连件，以及用于偏压管芯并互连在一起的施力机构。在说明性实施例中，底座包括以适于电连接到不同尺寸的互连件的通用图案布置的导体。因此，互连在基座上可以互换，用于使用相同的基底测试不同类型的骰子。基底上的导体可以形成在基座的平面有源表面上或具有不同尺寸的空腔的阶梯式有源表面上，用于安装不同尺寸的互连件。在替代实施例中，载体包括插入器。在第一插入器实施例中，插入器直接连接到外部测试电路，并且可以改变以适应不同尺寸的互连。在第二插入器实施例中，插入器连接到基座上的导体，并使基座适配于不同大小的互连使用。

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