专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20120132879A1 NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20120132879A1
公开(公告)日：2012-05-31
申请号：US13366544
申请日：2012-02-06
申请人： MASAHARU KINOSHITA , Yoshitaka Sasago , Norikatsu Takaura
发明人： MASAHARU KINOSHITA , Yoshitaka Sasago , Norikatsu Takaura
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/1675 , Y10S438/90
摘要： Provided is a nonvolatile memory device including a phase-change memory configured with cross-point memory cells in which memory elements formed of a phase-change material and selection elements formed with a diode are combined. A memory cell is configured with a memory element formed of a phase-change material and a selection element formed with a diode having a stacked structure of a first polycrystalline silicon film, a second polycrystalline silicon film, and a third polycrystalline silicon film. The memory cells are arranged at intersection points of a plurality of first metal wirings extending along a first direction with a plurality of third metal wirings extending along a second direction orthogonal to the first direction. An interlayer film is formed between adjacent selection elements and between adjacent memory elements, and voids are formed in the interlayer film provided between the adjacent memory elements.
摘要翻译：本发明提供一种非易失性存储装置，其包括：配置有交叉点存储单元的相变存储器，其中由相变材料形成的存储元件和由二极管形成的选择元件组合。存储单元配置有由相变材料形成的存储元件和由具有第一多晶硅膜，第二多晶硅膜和第三多晶硅膜的堆叠结构的二极管形成的选择元件。存储单元布置在沿着第一方向延伸的多个第一金属布线的交点和沿着与第一方向正交的第二方向延伸的多个第三金属布线。在相邻的选择元件之间和相邻的存储元件之间形成中间膜，并且在设置在相邻的存储元件之间的层间膜中形成空隙。

22. 发明授权

US08129705B2 Nonvolatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08129705B2
公开(公告)日：2012-03-06
申请号：US12434633
申请日：2009-05-02
申请人： Masaharu Kinoshita , Yoshitaka Sasago , Norikatsu Takaura
发明人： Masaharu Kinoshita , Yoshitaka Sasago , Norikatsu Takaura
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/1675 , Y10S438/90
摘要： Provided is a nonvolatile memory device including a phase-change memory configured with cross-point memory cells in which memory elements formed of a phase-change material and selection elements formed with a diode are combined. A memory cell is configured with a memory element formed of a phase-change material and a selection element formed with a diode having a stacked structure of a first polycrystalline silicon film, a second polycrystalline silicon film, and a third polycrystalline silicon film. The memory cells are arranged at intersection points of a plurality of first metal wirings extending along a first direction with a plurality of third metal wirings extending along a second direction orthogonal to the first direction. An interlayer film is formed between adjacent selection elements and between adjacent memory elements, and voids are formed in the interlayer film provided between the adjacent memory elements.
摘要翻译：本发明提供一种非易失性存储装置，其包括：配置有交叉点存储单元的相变存储器，其中由相变材料形成的存储元件和由二极管形成的选择元件组合。存储单元配置有由相变材料形成的存储元件和由具有第一多晶硅膜，第二多晶硅膜和第三多晶硅膜的堆叠结构的二极管形成的选择元件。存储单元布置在沿着第一方向延伸的多个第一金属布线的交点和沿着与第一方向正交的第二方向延伸的多个第三金属布线。在相邻的选择元件之间和相邻的存储元件之间形成中间膜，并且在设置在相邻的存储元件之间的层间膜中形成空隙。

23. 发明授权

US08830740B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08830740B2
公开(公告)日：2014-09-09
申请号：US13814104
申请日：2011-08-26
申请人： Yoshitaka Sasago , Hiroyuki Minemura , Takashi Kobayashi , Toshimichi Shintani , Satoru Hanzawa , Masaharu Kinoshita
发明人： Yoshitaka Sasago , Hiroyuki Minemura , Takashi Kobayashi , Toshimichi Shintani , Satoru Hanzawa , Masaharu Kinoshita
IPC分类号： G11C11/00 , H01L47/00 , G11C13/00
CPC分类号： G11C13/0004 , G11C2213/71 , G11C2213/72 , G11C2213/75 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/1233
摘要： The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line (2) and a bit line (3) and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out.
摘要翻译：本发明的目的是提高相变存储器的重写传输速率和可靠性。为了实现该目的，在串行（2）和位线（3）之间串联提供多个相变存储单元（SMC或USMC），并且具有并联连接的选择元件和存储元件彼此完全设置，之后，与数据模式对应的单元的一部分被重置。或者，执行相反的操作。

24. 发明申请

US20130141968A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20130141968A1
公开(公告)日：2013-06-06
申请号：US13814104
申请日：2011-08-26
申请人： Yoshitaka Sasago , Hiroyuki Minemura , Takashi Kobayashi , Toshimichi Shintani , Satoru Hanzawa , Masaharu Kinoshita
发明人： Yoshitaka Sasago , Hiroyuki Minemura , Takashi Kobayashi , Toshimichi Shintani , Satoru Hanzawa , Masaharu Kinoshita
IPC分类号： G11C13/00
CPC分类号： G11C13/0004 , G11C2213/71 , G11C2213/72 , G11C2213/75 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/1233
摘要： The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line (2) and a bit line (3) and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out.
摘要翻译：本发明的目的是提高相变存储器的重写传输速率和可靠性。为了实现该目的，在串行（2）和位线（3）之间串联提供多个相变存储单元（SMC或USMC），并且具有并联连接的选择元件和存储元件彼此完全设置，之后，与数据模式对应的单元的一部分被重置。或者，执行相反的操作。

25. 发明授权

US07767997B2 Semiconductor device with solid electrolyte switching 失效
标题翻译：具有固体电解质开关的半导体器件
公开(公告)号：US07767997B2
公开(公告)日：2010-08-03
申请号：US12169818
申请日：2008-07-09
申请人： Yoshitaka Sasago , Motoyasu Terao , Norikatsu Takaura , Yoshihisa Fujisaki , Tomoyuki Kodama , Nobuyuki Arasawa
发明人： Yoshitaka Sasago , Motoyasu Terao , Norikatsu Takaura , Yoshihisa Fujisaki , Tomoyuki Kodama , Nobuyuki Arasawa
IPC分类号： H01L29/06 , H01L29/08
CPC分类号： H01L45/1206 , G06N3/063 , G11C13/0011 , H01L45/085 , H01L45/142 , H01L45/146 , H01L45/1675
摘要： A nonvolatile, sophisticated semiconductor device with a small surface area and a simple structure capable of switching connections between three or more electrodes. In a semiconductor device at least one of the electrodes contains atoms such as copper or silver in the solid electrolyte capable of easily moving within the solid electrolyte, and those electrodes face each other and applying a voltage switches the voltage on and off by generating or annihilating the conductive path between the electrodes. Moreover applying a voltage to a separate third electrode can annihilate the conductive path formed between two electrodes without applying a voltage to the two electrode joined by the conductive path.
摘要翻译：具有小表面积的非易失性，复杂的半导体器件和能够切换三个或更多个电极之间的连接的简单结构。在半导体器件中，电极中的至少一个在固体电解质中含有诸如铜或银之类的原子，能够容易地在固体电解质内移动，并且这些电极彼此面对并且施加电压通过产生或消除电压来开启和关闭电压电极之间的导电路径。此外，向单独的第三电极施加电压可以消除在两个电极之间形成的导电路径，而不向由导电路径连接的两个电极施加电压。

26. 发明申请

US20090014770A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090014770A1
公开(公告)日：2009-01-15
申请号：US12169789
申请日：2008-07-09
申请人： Motoyasu Terao , Hideyuki Matsuoka , Naohiko Irie , Yoshitaka Sasago , Riichiro Takemura , Norikatsu Takaura
发明人： Motoyasu Terao , Hideyuki Matsuoka , Naohiko Irie , Yoshitaka Sasago , Riichiro Takemura , Norikatsu Takaura
IPC分类号： H01L29/00
CPC分类号： H01L45/145 , G11C11/5614 , G11C13/0011 , G11C2213/11 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146
摘要： A technique that can realize high integration even for multilayered three-dimensional structures at low costs by improving the performance of the semiconductor device having recording or switching functions by employing a device structure that enables high precision controlling of the movement of ions in the solid electrolyte. The semiconductor element of the device is formed as follows; two or more layers are deposited with different components respectively between a pair of electrodes disposed separately in the vertical (z-axis) direction, then a pulse voltage is applied between those electrodes to form a conductive path. The resistance value of the path changes according to an information signal. Furthermore, a region is formed at a middle part of the conductive path. The region is used to accumulate a component that improves the conductivity of the path, thereby enabling the resistance value (rate) to response currently to the information signal. More preferably, an electrode should also be formed at least in either the x-axis or y-axis direction to apply a control voltage to the electrode.
摘要翻译：通过采用能够高精度地控制固体电解质中的离子的运动的装置结构，通过提高具有记录或切换功能的半导体器件的性能，可以以低成本实现多层次三维结构的高集成度的技术。器件的半导体元件如下形成; 分别在垂直（z轴）方向上分开设置的一对电极之间分别沉积两层或更多层，然后在这些电极之间施加脉冲电压以形成导电路径。路径的电阻值根据信息信号而变化。此外，在导电路径的中间部分形成区域。该区域用于累积改善路径的导电性的分量，从而使电阻值（速率）能够当前响应于信息信号。更优选地，电极也应至少形成在x轴方向或y轴方向上，以向电极施加控制电压。

27. 发明授权

US07829930B2 Semiconductor device with ion movement control 有权
标题翻译：半导体器件具有离子运动控制
公开(公告)号：US07829930B2
公开(公告)日：2010-11-09
申请号：US12169789
申请日：2008-07-09
申请人： Motoyasu Terao , Hideyuki Matsuoka , Naohiko Irie , Yoshitaka Sasago , Riichiro Takemura , Norikatsu Takaura
发明人： Motoyasu Terao , Hideyuki Matsuoka , Naohiko Irie , Yoshitaka Sasago , Riichiro Takemura , Norikatsu Takaura
IPC分类号： H01L27/108
CPC分类号： H01L45/145 , G11C11/5614 , G11C13/0011 , G11C2213/11 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146
摘要： A technique that can realize high integration even for multilayered three-dimensional structures at low costs by improving the performance of the semiconductor device having recording or switching functions by employing a device structure that enables high precision controlling of the movement of ions in the solid electrolyte. The semiconductor element of the device is formed as follows; two or more layers are deposited with different components respectively between a pair of electrodes disposed separately in the vertical (z-axis) direction, then a pulse voltage is applied between those electrodes to form a conductive path. The resistance value of the path changes according to an information signal. Furthermore, a region is formed at a middle part of the conductive path. The region is used to accumulate a component that improves the conductivity of the path, thereby enabling the resistance value (rate) to response currently to the information signal. More preferably, an electrode should also be formed at least in either the x-axis or y-axis direction to apply a control voltage to the electrode.
摘要翻译：通过采用能够高精度地控制固体电解质中的离子的运动的装置结构，通过提高具有记录或切换功能的半导体器件的性能，可以以低成本实现多层次三维结构的高集成度的技术。器件的半导体元件如下形成; 分别在垂直（z轴）方向上分开设置的一对电极之间分别沉积两层或更多层，然后在这些电极之间施加脉冲电压以形成导电路径。路径的电阻值根据信息信号而变化。此外，在导电路径的中间部分形成区域。该区域用于累积改善路径的导电性的分量，从而使电阻值（速率）能够当前响应于信息信号。更优选地，电极也应至少形成在x轴方向或y轴方向上，以向电极施加控制电压。

28. 发明授权

US08730717B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08730717B2
公开(公告)日：2014-05-20
申请号：US13104005
申请日：2011-05-09
申请人： Satoru Hanzawa , Yoshitaka Sasago
发明人： Satoru Hanzawa , Yoshitaka Sasago
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C2213/71 , G11C2213/72 , G11C2213/75 , G11C2213/78 , H01L27/2454 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/124 , H01L45/144
摘要： A semiconductor device has multiple memory cell groups arranged at intersections between multiple word lines and multiple bit lines intersecting the word lines. The memory cell groups each have first and second memory cells connected in series. Each of the first and the second memory cells has a select transistor and a resistive storage device connected in parallel. The gate electrode of the select transistor in the first memory cell is connected with a first gate line, and the gate electrode of the select transistor in the second memory cell is connected to a second gate line. A first circuit block for driving the word lines (word driver group WDBK) is arranged between a second circuit block for driving the first and second gate lines (phase-change-type chain cell control circuit PCCCTL) and multiple memory cell groups (memory cell array MA).
摘要翻译：半导体器件具有布置在多个字线和与字线相交的多个位线之间的交叉处的多个存储单元组。存储单元组各自具有串联连接的第一和第二存储器单元。第一和第二存储单元中的每一个具有并联连接的选择晶体管和电阻存储器件。第一存储单元中的选择晶体管的栅电极与第一栅极线连接，第二存储单元中的选择晶体管的栅电极连接到第二栅极线。用于驱动字线的第一电路块（字驱动器组WDBK）被布置在用于驱动第一和第二栅极线（相变型链单元控制电路PCCCTL）的第二电路块和多个存储单元组阵列MA）。

29. 发明授权

US08699262B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08699262B2
公开(公告)日：2014-04-15
申请号：US13270299
申请日：2011-10-11
申请人： Takao Watanabe , Satoru Hanzawa , Yoshitaka Sasago
发明人： Takao Watanabe , Satoru Hanzawa , Yoshitaka Sasago
IPC分类号： G11C11/24
CPC分类号： H01L45/06 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2213/71 , G11C2213/72 , G11C2213/75 , G11C2213/78 , G11C2213/79 , H01L27/2481
摘要： Adverse effects of a parasitic resistance and a parasitic capacitance of a driver circuit to a memory cell causes problems of thermal disturbance to a not-selected cell, unevenness of application voltage, degradation of a memory element in reading. A capacitor (C) is provided above or beneath a memory cell (MC) that includes a memory element to which a current write memory information and a selection element connected to the memory element. A charge stored in this capacitor writes to the memory element.
摘要翻译：驱动电路的寄生电阻和寄生电容对存储单元的不利影响引起对未选择单元的热扰动，施加电压的不均匀性，读取中存储元件的劣化的问题。电容器（C）设置在存储单元（MC）的上方或下方，存储单元（MC）包括与存储元件连接的当前写入存储器信息和选择元件的存储元件。存储在该电容器中的电荷写入存储器元件。

30. 发明申请

US20120087178A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120087178A1
公开(公告)日：2012-04-12
申请号：US13270299
申请日：2011-10-11
申请人： Takao WATANABE , Satoru Hanzawa , Yoshitaka Sasago
发明人： Takao WATANABE , Satoru Hanzawa , Yoshitaka Sasago
IPC分类号： G11C11/24
CPC分类号： H01L45/06 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2213/71 , G11C2213/72 , G11C2213/75 , G11C2213/78 , G11C2213/79 , H01L27/2481
摘要： Adverse effects of a parasitic resistance and a parasitic capacitance of a driver circuit to a memory cell causes problems of thermal disturbance to a not-selected cell, unevenness of application voltage, degradation of a memory element in reading. A capacitor (C) is provided above or beneath a memory cell (MC) that includes a memory element to which a current write memory information and a selection element connected to the memory element. A charge stored in this capacitor writes to the memory element.
摘要翻译：驱动电路的寄生电阻和寄生电容对存储单元的不利影响引起对未选择单元的热扰动，施加电压的不均匀性，读取中存储元件的劣化的问题。电容器（C）设置在存储单元（MC）的上方或下方，存储单元（MC）包括与存储元件连接的当前写入存储器信息和选择元件的存储元件。存储在该电容器中的电荷写入存储器元件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式