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21. 发明授权

US08767452B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08767452B2
公开(公告)日：2014-07-01
申请号：US13418651
申请日：2012-03-13
申请人： Masaru Kito , Tomoko Fujiwara , Hideaki Aochi
发明人： Masaru Kito , Tomoko Fujiwara , Hideaki Aochi
IPC分类号： G11C11/14 , G11C11/00
CPC分类号： H01L27/11565 , G11C5/025 , H01L27/11582 , H01L29/7926
摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a charge storage layer, a tunneling layer, a dividing trench and a first heating unit. The stacked body includes a plurality of first insulating films stacked alternately with a plurality of electrode films. The semiconductor pillar pierces the stacked body. The charge storage layer is provided between the electrode films and the semiconductor pillar. The tunneling layer is provided between the charge storage layer and the semiconductor pillar. The dividing trench is provided between the semiconductor pillars in one direction orthogonal to a stacking direction of the stacked body to divide the electrode films. The first heating unit is provided in an interior of the dividing trench.
摘要翻译：根据一个实施例，半导体存储器件包括堆叠体，半导体柱，电荷存储层，隧道层，分隔沟槽和第一加热单元。层叠体包括与多个电极膜交替堆叠的多个第一绝缘膜。半导体柱穿透层叠体。电荷存储层设置在电极膜和半导体柱之间。隧道层设置在电荷存储层和半导体柱之间。在与层叠体的堆叠方向正交的一个方向上的半导体柱之间设置分割沟槽，以分割电极膜。第一加热单元设置在分隔沟槽的内部。

22. 发明授权

US08766351B2 Semiconductor storage device and manufacturing method of semiconductor storage device 有权
标题翻译：半导体存储装置及半导体存储装置的制造方法
公开(公告)号：US08766351B2
公开(公告)日：2014-07-01
申请号：US13112345
申请日：2011-05-20
申请人： Takeshi Imamura , Yoshiaki Fukuzumi , Hideaki Aochi , Masaru Kito , Tomoko Fujiwara , Kaori Kawasaki , Ryouhei Kirisawa
发明人： Takeshi Imamura , Yoshiaki Fukuzumi , Hideaki Aochi , Masaru Kito , Tomoko Fujiwara , Kaori Kawasaki , Ryouhei Kirisawa
IPC分类号： H01L29/788
CPC分类号： H01L27/11556 , H01L29/42324 , H01L29/7889
摘要： According to one embodiment, a columnar semiconductor, a floating gate electrode formed on a side surface of the columnar semiconductor via a tunnel dielectric film, and a control gate electrode formed to surround the floating gate electrode via a block dielectric film are provided.
摘要翻译：根据一个实施例，提供了柱状半导体，通过隧道电介质膜形成在柱状半导体的侧表面上的浮栅电极和通过块状电介质膜包围浮置栅电极的控制栅电极。

23. 发明授权

US08629492B2 Shift register memory 失效
标题翻译：移位寄存器存储器
公开(公告)号：US08629492B2
公开(公告)日：2014-01-14
申请号：US13405692
申请日：2012-02-27
申请人： Yoshiaki Fukuzumi , Hideaki Aochi , Tomoko Fujiwara
发明人： Yoshiaki Fukuzumi , Hideaki Aochi , Tomoko Fujiwara
IPC分类号： H01L29/762
CPC分类号： B82Y10/00 , G11C19/00 , G11C19/282 , G11C19/38 , H01L27/1052 , H01L27/1057 , H01L27/115 , H01L27/11517 , H01L29/0676 , H01L29/068 , H01L29/788
摘要： In one embodiment, a shift register memory includes a substrate, and a channel layer provided on the substrate, and having a helical shape rotating around an axis which is perpendicular to a surface of the substrate. The memory further includes at least three control electrodes provided on the substrate, extending in a direction parallel to the axis, and to be used to transfer charges in the channel layer.
摘要翻译：在一个实施例中，移位寄存器存储器包括衬底和设置在衬底上的沟道层，并且具有围绕垂直于衬底表面的轴线旋转的螺旋形状。存储器还包括设置在基板上的至少三个控制电极，其在平行于该轴线的方向上延伸，并用于在沟道层中传送电荷。

24. 发明授权

US08436414B2 Non-volatile semiconductor stacked memory device having two semiconductor pillars in a through hole and method for manufacturing same 有权
标题翻译：在通孔中具有两个半导体柱的非易失性半导体堆叠式存储器件及其制造方法
公开(公告)号：US08436414B2
公开(公告)日：2013-05-07
申请号：US12706127
申请日：2010-02-16
申请人： Hiroyasu Tanaka , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Masaru Kito , Yoshiaki Fukuzumi , Yosuke Komori , Megumi Ishiduki , Tomoko Fujiwara , Junya Matsunami , Ryouhei Kirisawa
发明人： Hiroyasu Tanaka , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Masaru Kito , Yoshiaki Fukuzumi , Yosuke Komori , Megumi Ishiduki , Tomoko Fujiwara , Junya Matsunami , Ryouhei Kirisawa
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/11578 , H01L27/11582 , H01L29/66833
摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate, the stacked body having electrode films and insulating films being alternately stacked; a first and second semiconductor pillars; and a first and second charge storage layers. The first and second semiconductor pillars are provided inside a through hole penetrating through the stacked body in a stacking direction of the stacked body. The through hole has a cross section of an oblate circle, when cutting in a direction perpendicular to the stacking direction. The first and second semiconductor pillars face each other in a major axis direction of the first oblate circle. The first and second semiconductor pillars extend in the stacking direction. The first and second charge storage layers are provided between the electrode film and the first and second semiconductor pillars, respectively.
摘要翻译：非易失性半导体存储器件包括：半导体衬底; 设置在所述半导体基板上的层叠体，具有交替堆叠的电极膜和绝缘膜的层叠体，第一和第二半导体柱; 以及第一和第二电荷存储层。第一半导体柱和第二半导体柱设置在层叠体的层叠方向上贯穿层叠体的贯通孔内。当沿垂直于堆叠方向的方向切割时，通孔具有扁圆形的横截面。第一和第二半导体柱在第一扁圆的长轴方向上彼此面对。第一和第二半导体柱沿层叠方向延伸。第一和第二电荷存储层分别设置在电极膜和第一和第二半导体柱之间。

25. 发明授权

US08189371B2 Nonvolatile semiconductor memory device and method for driving same 有权
标题翻译：非易失性半导体存储器件及其驱动方法
公开(公告)号：US08189371B2
公开(公告)日：2012-05-29
申请号：US12851002
申请日：2010-08-05
申请人： Ryota Katsumata , Hideaki Aochi , Hiroyasu Tanaka , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Ryota Katsumata , Hideaki Aochi , Hiroyasu Tanaka , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： G11C11/14
CPC分类号： G11C16/0483 , G11C16/06 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a stacked body, a through-hole, a semiconductor pillar, and a charge storage film. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. The through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in the through-hole. The charge storage film is provided between the electrode films and the semiconductor pillar. Memory cells are formed at each intersection between the electrode films and the semiconductor pillar. The control circuit writs a first value to at least some of the memory cells, performs an erasing operation of the first value from the memory cell written with the first value, reads data stored in the memory cell having undergone the erasing operation, and sets the memory cell to be unusable in a case that the first value is read from the memory cell.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括存储单元阵列和控制电路。存储单元阵列包括层叠体，通孔，半导体柱和电荷存储膜。层叠体包括交替层叠有多个电极膜的多个绝缘膜。通孔形成在堆叠体中以沿堆叠方向对齐。半导体柱埋在通孔中。电荷存储膜设置在电极膜和半导体柱之间。在电极膜和半导体柱之间的每个交叉处形成存储单元。控制电路将第一值写入至少部分存储单元，从写入第一值的存储单元执行第一值的擦除操作，读取存储在经过擦除操作的存储单元中的数据，并将在从存储器单元读取第一值的情况下，存储器单元不可用。

26. 发明授权

US08188530B2 Nonvolatile semiconductor memory device and method for manufacturing same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08188530B2
公开(公告)日：2012-05-29
申请号：US12728727
申请日：2010-03-22
申请人： Hiroyasu Tanaka , Ryota Katsumata , Hideaki Aochi , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Hiroyasu Tanaka , Ryota Katsumata , Hideaki Aochi , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： H01L21/8239 , H01L29/78 , H01L27/088
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： A semiconductor memory device provided with a cell array section and a peripheral circuit section, the device includes: a back gate electrode; a stacked body provided on the back gate electrode; a plurality of semiconductor pillars extending in a stacking direction; connection members, each of the connection members connecting one of the semiconductor pillars to another one of the semiconductor pillars; a back-gate electrode contact applying a potential to the back gate electrode; a gate electrode provided in the peripheral circuit section; and a gate electrode contact applying a potential to the gate electrode, the back gate electrode and the gate electrode respectively including: a lower semiconductor layer; a conductive layer provided on the lower semiconductor layer; and an upper semiconductor layer provided on the conductive layer, the connection members being provided in or on the upper semiconductor layer, the back-gate electrode contact and the gate electrode contact being in contact with the conductive layer.
摘要翻译：一种设置有单元阵列部分和外围电路部分的半导体存储器件，该器件包括：背栅电极; 设置在所述背栅电极上的层叠体; 沿层叠方向延伸的多个半导体柱; 连接构件，每个连接构件将半导体柱之一连接到另一个半导体柱; 向所述背栅电极施加电位的背栅极电极接触; 设置在所述外围电路部中的栅电极; 以及向所述栅电极，所述背栅电极和所述栅电极施加电位的栅电极接触部，分别包括：下半导体层; 设置在下半导体层上的导电层; 以及设置在所述导电层上的上半导体层，所述连接构件设置在所述上半导体层中或所述上半导体层上，所述背栅电极接触和所述栅电极接触与所述导电层接触。

27. 发明申请

US20110188321A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME 有权
标题翻译：非易失性半导体存储器件及其驱动方法
公开(公告)号：US20110188321A1
公开(公告)日：2011-08-04
申请号：US13018786
申请日：2011-02-01
申请人： Masaru Kito , Tomoko Fujiwara , Yoshimasa Mikajiri
发明人： Masaru Kito , Tomoko Fujiwara , Yoshimasa Mikajiri
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： G11C16/04 , H01L29/792
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a charge storage film, a first insulating film provided adjacent to one surface of the charge storage film, a second insulating film provided adjacent to one other surface of the charge storage film, a semiconductor portion provided adjacent to the first insulating film and a plurality of electrode portions provided adjacent to the second insulating film. The control unit performs a control of applying a first voltage to electrode portions adjacent to each other in one direction at different timing respectively, in an erasing. The erasing is performed by at least one selected from injecting electron holes into the charge storage film and removing electrons from the charge storage film. The first voltage is applied from one of the electrode portions to the charge storage film to be erased.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括存储器单元和控制单元。存储单元包括电荷存储膜，邻近电荷存储膜的一个表面设置的第一绝缘膜，与电荷存储膜的另一个表面相邻设置的第二绝缘膜，邻近第一绝缘膜设置的半导体部分以及与第二绝缘膜相邻设置的多个电极部。控制单元执行对在擦除中分别在不同时刻在一个方向上彼此相邻的电极部分施加第一电压的控制。通过从电荷储存膜中注入电子空穴和从电荷存储膜去除电子中的至少一种进行擦除。第一电压从电极部分之一施加到要擦除的电荷存储膜。

28. 发明申请

US20110075481A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110075481A1
公开(公告)日：2011-03-31
申请号：US12694677
申请日：2010-01-27
申请人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Tomoko Fujiwara , Megumi Ishiduki , Yosuke Komori , Yoshimasa Mikajiri , Shigeto Oota , Ryouhei Kirisawa , Hideaki Aochi
发明人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Tomoko Fujiwara , Megumi Ishiduki , Yosuke Komori , Yoshimasa Mikajiri , Shigeto Oota , Ryouhei Kirisawa , Hideaki Aochi
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C11/34 , G11C5/02 , G11C16/26
摘要： A nonvolatile semiconductor memory device comprises: a bit line; a source line; a memory string having a plurality of electrically data-rewritable memory transistors connected in series; a first select transistor provided between one end of the memory string and the bit line; a second select transistor provided between the other end of the memory string and the source line; and a control circuit configured to control a read operation. A plurality of the memory strings connected to one bit line via a plurality of the first select transistors. During reading of data from a selected one of the memory strings, the control circuit renders conductive the first select transistor connected to an unselected one of the memory strings and renders non-conductive the second select transistor connected to unselected one of the memory strings.
摘要翻译：非易失性半导体存储器件包括：位线; 源线; 具有串联连接的多个电数据可重写存储晶体管的存储器串; 设置在存储器串的一端和位线之间的第一选择晶体管; 设置在存储器串的另一端与源极线之间的第二选择晶体管; 以及控制电路，被配置为控制读取操作。经由多个第一选择晶体管连接到一个位线的多个存储器串。在从选择的一个存储器串读取数据期间，控制电路使连接到未选择的一个存储器串的第一选择晶体管导通，并且使第二选择晶体管连接到未选择的一个存储器串。

29. 发明申请

US20110049608A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20110049608A1
公开(公告)日：2011-03-03
申请号：US12723981
申请日：2010-03-15
申请人： Masaru KIDOH , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Tomoko Fujiwara , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Masaru KIDOH , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Tomoko Fujiwara , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/66833 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： A memory string comprises: a first semiconductor layer including a columnar portion extending in a stacking direction on a substrate; a first charge storage layer surrounding the columnar portion; and a plurality of first conductive layers stacked on the substrate so as to surround the first charge storage layer. A select transistor comprises: a second semiconductor layer in contact with an upper surface of the columnar portion and extending in the stacking direction; a second charge storage layer surrounding the second semiconductor layer; and a second conductive layer deposited above the first conductive layer to surround the second charge storage layer. The second charge storage layer is formed from a layer downward of the second conductive layer to an upper end vicinity of the second conductive layer, and is not formed in a layer upward of the upper end vicinity.
摘要翻译：存储器串包括：第一半导体层，包括在基板上沿堆叠方向延伸的柱状部分; 围绕所述柱状部分的第一电荷存储层; 以及堆叠在所述基板上以围绕所述第一电荷存储层的多个第一导电层。选择晶体管包括：与柱状部分的上表面接触并沿堆叠方向延伸的第二半导体层; 围绕所述第二半导体层的第二电荷存储层; 以及沉积在所述第一导电层上方以围绕所述第二电荷存储层的第二导电层。第二电荷存储层由第二导电层向下的层向第二导电层的上端附近形成，并且不形成在上端附近的上方。

30. 发明申请

US20110013454A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110013454A1
公开(公告)日：2011-01-20
申请号：US12726858
申请日：2010-03-18
申请人： Tomoo Hishida , Yoshihisa Iwata , Megumi Ishiduki , Ryota Katsumata , Yoshiaki Fukuzumi , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Junya Matsunami , Tomoko Fujiwara , Hideaki Aochi , Ryouhel Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Tomoo Hishida , Yoshihisa Iwata , Megumi Ishiduki , Ryota Katsumata , Yoshiaki Fukuzumi , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Junya Matsunami , Tomoko Fujiwara , Hideaki Aochi , Ryouhel Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C5/025 , G11C5/02 , G11C5/04 , G11C16/0483 , H01L27/11573 , H01L27/11578 , H01L27/11582
摘要： A nonvolatile semiconductor memory device comprises: a plurality of first memory strings; a first select transistor having one end thereof connected to one end of the first memory strings; a first line commonly connected to the other end of a plurality of the first select transistors; a switch circuit having one end thereof connected to the first line; and a second line commonly connected to the other end of a plurality of the switch circuits. The switch circuit controls electrical connection between the second line and the first line.
摘要翻译：非易失性半导体存储器件包括：多个第一存储器串; 第一选择晶体管，其一端连接到第一存储器串的一端; 通常连接到多个第一选择晶体管的另一端的第一线; 开关电路，其一端连接到第一线; 以及通常连接到多个开关电路的另一端的第二线。开关电路控制第二线和第一线之间的电连接。

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