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21. 发明授权

US06512715B2 Semiconductor memory device operating with low power consumption 有权
标题翻译：半导体存储器件以低功耗运行
公开(公告)号：US06512715B2
公开(公告)日：2003-01-28
申请号：US09987837
申请日：2001-11-16
申请人： Takeo Okamoto , Tadaaki Yamauchi , Junko Matsumoto
发明人： Takeo Okamoto , Tadaaki Yamauchi , Junko Matsumoto
IPC分类号： G11C700
CPC分类号： G11C5/147
摘要： In a low power consumption mode, an internal power supply circuit produces an internal power supply voltage by electrically coupling an internal power supply line to either an external power supply line or a ground line through a transistor. Accordingly, in the low power consumption mode, supply of an operating current to a reference voltage generation circuit, a buffer circuit, an internal power supply voltage generation circuit and a voltage booster circuit is discontinued, allowing for reduction in power consumption of the internal power supply circuit itself.
摘要翻译：在低功耗模式中，内部电源电路通过将内部电源线通过晶体管电连接到外部电源线或接地线来产生内部电源电压。因此，在低功耗模式中，停止向参考电压产生电路，缓冲电路，内部电源电压产生电路和升压电路的供电，允许内部电力的功耗降低供电电路本身。

22. 发明授权

US06744298B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06744298B2
公开(公告)日：2004-06-01
申请号：US10209906
申请日：2002-08-02
申请人： Tadaaki Yamauchi , Takeo Okamoto , Junko Matsumoto
发明人： Tadaaki Yamauchi , Takeo Okamoto , Junko Matsumoto
IPC分类号： H03L500
CPC分类号： G11C11/4072 , G11C7/20
摘要： In the output circuit, at a subsequent stage of a gate circuit operating with a power supply voltage related to a first power supply voltage, a latch circuit formed of an inverter circuit and a MOS transistor is arranged, and is supplied with a second power supply voltage as an operating power supply voltage. An output buffer circuit is driven in accordance with an output signal of the latch circuit. When the first power supply voltage is powered down, the latch circuit receiving and operating with the second power supply voltage holds a signal voltage to be attained in a standby state and thus the output buffer circuit is reliably held in an output high impedance state. In a semiconductor device of a double power supply configuration, even when one power supply is powered down, the output buffer circuit can reliably be set to an output high impedance state.
摘要翻译：在输出电路中，在以与第一电源电压相关的电源电压工作的门电路的后续阶段，布置由逆变器电路和MOS晶体管形成的锁存电路，并且被提供有第二电源电压作为工作电源电压。根据锁存电路的输出信号驱动输出缓冲电路。当第一电源电压断电时，以第二电源电压接收和操作的锁存电路在备用状态下保持要获得的信号电压，从而将输出缓冲电路可靠地保持在输出高阻抗状态。在双电源配置的半导体器件中，即使当一个电源断电时，输出缓冲电路也可以可靠地设置为输出高阻抗状态。

23. 发明授权

US06724223B2 Semiconductor device used in two systems having different power supply voltages 有权
标题翻译：在具有不同电源电压的两个系统中使用的半导体器件
公开(公告)号：US06724223B2
公开(公告)日：2004-04-20
申请号：US10287643
申请日：2002-11-05
申请人： Tetsuichiro Ichiguchi , Tsutomu Nagasawa , Tadaaki Yamauchi , Zengcheng Tian , Makoto Suwa , Junko Matsumoto , Takeo Okamoto , Hideki Yonetani
发明人： Tetsuichiro Ichiguchi , Tsutomu Nagasawa , Tadaaki Yamauchi , Zengcheng Tian , Makoto Suwa , Junko Matsumoto , Takeo Okamoto , Hideki Yonetani
IPC分类号： H03K190175
CPC分类号： G11C7/225 , G11C5/14 , G11C7/22 , G11C11/4074 , G11C11/4076 , H01L27/0255
摘要： A clock buffer of a DRAM includes: a first NAND gate which is driven by a first internal power supply voltage (2.5 V) and which determines the level of an input clock signal if the DRAM is used for a TTL-system interface (MLV=2.5 V); and a second NAND gate which is driven by a second internal power supply voltage (1.8 V) and which determines the level of the input clock signal if the DRAM is used for a 1.8 V-system interface (MLV=0 V). Accordingly, in each of the first and second NAND gates, sizes of four MOS transistors can be set at optimum values, respectively.
摘要翻译： DRAM的时钟缓冲器包括：第一NAND门，其由第一内部电源电压（2.5V）驱动，并且如果DRAM用于TTL系统接口，则确定输入时钟信号的电平（MLV = 2.5 V）; 以及第二NAND门，其由第二内部电源电压（1.8V）驱动，并且如果DRAM用于1.8V系统接口（MLV = 0V），则确定输入时钟信号的电平。因此，在第一和第二NAND门的每一个中，四个MOS晶体管的尺寸可以分别被设定为最佳值。

24. 发明授权

US06717460B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06717460B2
公开(公告)日：2004-04-06
申请号：US10211289
申请日：2002-08-05
申请人： Tadaaki Yamauchi , Takeo Okamoto , Junko Matsumoto , Zengcheng Tian
发明人： Tadaaki Yamauchi , Takeo Okamoto , Junko Matsumoto , Zengcheng Tian
IPC分类号： G05F110
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/1087 , G11C7/20 , G11C11/4072 , G11C11/4074
摘要： A level conversion circuit is provided, at an output, with an initialization circuit for setting the output signal of the level conversion circuit for generating a power cut enable signal controlling a deep power down mode to a predetermined inactive state upon power up. The initialization circuit is constituted by, for example, a capacitive element connected to the output node of the level conversion circuit to pull up the voltage of the output node upon power up, and a latch circuit latching the voltage level of the output node. When power is on, the power cut enable signal is forcibly inactivated by the initialization circuit to generate a periphery power supply voltage. The internal node of the level conversion circuit is initialized according to the output signal of a control circuit receiving the periphery power supply voltage as an operating power supply voltage. In semiconductor memory device having a deep power down mode, an internal voltage is generated reliably and properly upon power up of an internal voltage.
摘要翻译：在输出端提供电平转换电路，该初始化电路用于设置电平转换电路的输出信号，用于在上电时产生控制深度掉电模式至预定非活动状态的掉电使能信号。初始化电路例如由与电平转换电路的输出节点连接的电容元件构成，以在上电时上拉输出节点的电压，以及锁存电路来锁存输出节点的电压电平。当电源接通时，断电启动信号被初始化电路强制停用，以产生外围电源电压。电平转换电路的内部节点根据接收外围电源电压的控制电路的输出信号作为工作电源电压进行初始化。在具有深度掉电模式的半导体存储器件中，在内部电压上电时可靠且可靠地产生内部电压。

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