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21. 发明申请

US20080117608A1 Printed circuit board and fabricating method thereof 审中-公开
标题翻译：印刷电路板及其制造方法
公开(公告)号：US20080117608A1
公开(公告)日：2008-05-22
申请号：US11974962
申请日：2007-10-17
申请人： Ho-Seong Seo , Young-Min Lee , Shi-Yun Cho , Youn-Ho Choi , Sang-Hyun Kim
发明人： Ho-Seong Seo , Young-Min Lee , Shi-Yun Cho , Youn-Ho Choi , Sang-Hyun Kim
IPC分类号： H05K1/18 , H05K1/02 , H05K3/10 , H05K3/42
CPC分类号： H05K1/185 , H01L24/19 , H01L24/82 , H01L25/0657 , H01L2224/04105 , H01L2224/73267 , H01L2224/82039 , H01L2224/92244 , H01L2225/06524 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/14 , H01L2924/15153 , H05K3/0035 , H05K3/4614 , H05K3/4652 , H05K2201/09127 , Y10T29/49165
摘要： Disclosed are a multi-layer PCB and a fabricating method thereof. The multi-layer PCB includes: a core; a plurality of insulation layers and a plurality of conductive pattern layers alternatively stacked on both sides of the core; and a plurality of via holes formed through the core and the insulation layers. The fabricating method may includes the steps of: forming a conductive pattern layer on each of both sides of a core, and forming via holes through the core; attaching a double-stick tape with weak adhesive strength to a portion of each of a upper surface and a lower surface of the core; and forming an insulation layer on each of a upper surface and a lower surface of the core to cover the double-stick tapes, and forming a conductive pattern layer on each of the insulation layers.
摘要翻译：公开了一种多层PCB及其制造方法。多层PCB包括：核心; 多个绝缘层和交替堆叠在芯的两侧上的多个导电图案层; 以及形成在所述芯和所述绝缘层上的多个通孔。制造方法可以包括以下步骤：在芯的两侧的每一侧上形成导电图案层，并且形成穿过芯的通孔; 将具有弱粘合强度的双面胶带附着到芯的上表面和下表面的每一个的一部分; 并且在所述芯的上表面和下表面的每一个上形成绝缘层以覆盖所述双色带，并且在每个所述绝缘层上形成导电图案层。

22. 发明授权

US07342631B2 Liquid crystal display device and method of fabricating the same 有权
标题翻译：液晶显示装置及其制造方法
公开(公告)号：US07342631B2
公开(公告)日：2008-03-11
申请号：US10863235
申请日：2004-06-09
申请人： Sang Hyun Kim
发明人： Sang Hyun Kim
IPC分类号： G02F1/1343
CPC分类号： G02F1/136227
摘要： A method of fabricating a liquid crystal display device includes forming a data bus line on a substrate, forming a preliminary interlayer insulating layer having a first thickness on the substrate including the data bus line, forming an interlayer insulating layer by etching the preliminary interlayer insulating layer to a second thickness less than the first thickness, the interlayer insulating layer having a planarized surface, sequentially forming a semiconductor layer, a gate insulating layer, and a gate electrode on the interlayer insulating layer, forming a passivation layer on the substrate, forming a plurality of contact holes exposing portions of the data bus line and the semiconductor layer by etching portions of the passivation layer, and forming a pixel electrode on the passivation layer.
摘要翻译：一种液晶显示装置的制造方法，其特征在于，在基板上形成数据总线，在包括所述数据总线的基板上形成具有第一厚度的预备层间绝缘层，通过蚀刻所述初始层间绝缘层所述层间绝缘层具有平坦化表面，在所述层间绝缘层上依次形成半导体层，栅极绝缘层和栅电极，在所述基板上形成钝化层，形成所述第一厚度，多个接触孔通过蚀刻钝化层的部分而暴露数据总线和半导体层的部分，以及在钝化层上形成像素电极。

23. 发明申请

US20070228966A1 Plasma display panel having electrodes covered by a dielectric layer 失效
标题翻译：等离子体显示面板，其电极由电介质层覆盖
公开(公告)号：US20070228966A1
公开(公告)日：2007-10-04
申请号：US11727475
申请日：2007-03-27
申请人： Jung-Suk Song , Ki-Dong Kim , Seong-Hun Choo , Joon-Hyeong Kim , Sang-Hyun Kim , Bo-Won Lee
发明人： Jung-Suk Song , Ki-Dong Kim , Seong-Hun Choo , Joon-Hyeong Kim , Sang-Hyun Kim , Bo-Won Lee
IPC分类号： H01J17/49
CPC分类号： H01J11/38 , H01J9/02 , H01J11/12 , H01J2211/245 , H01J2211/326
摘要： A plasma display panel having a uniformly distributed firing voltage despite of irregular discharge gaps, the plasma display panel including a first substrate, a second substrate facing the first substrate, barrier ribs between the first and second substrates to define discharge cells, address electrodes corresponding to the discharge cells and extending in a first direction, first and second electrodes respectively extending in a second direction crossing the first direction and formed on any one of the first and second substrates, corresponding to the discharge cells, and a dielectric layer covering the first and second electrodes, where the first and second electrodes are spaced apart from each other to form a discharge gap having distances, the dielectric layer having varied permittivities according to distances of the discharge gaps to improve discharge uniformity according to the distances of the discharge gaps.
摘要翻译：一种具有均匀分布的点火电压的等离子体显示面板，尽管有不规则的放电间隙，等离子体显示面板包括第一衬底，面对第一衬底的第二衬底，第一和第二衬底之间的阻挡肋，以限定放电单元，对应于放电单元并且沿第一方向延伸，第一和第二电极分别沿与第一方向交叉的第二方向延伸并形成在对应于放电单元的第一和第二基板中的任何一个上，以及覆盖第一和第二电极，其中第一和第二电极彼此间隔开以形成具有距离的放电间隙，介电层根据放电间隙的距离具有不同的介电常数，以根据放电间隙的距离改善放电均匀性。

24. 发明授权

US07259103B2 Fabrication method of polycrystalline silicon TFT 有权
标题翻译：多晶硅TFT的制造方法
公开(公告)号：US07259103B2
公开(公告)日：2007-08-21
申请号：US10663805
申请日：2003-09-17
申请人： Sang Hyun Kim
发明人： Sang Hyun Kim
IPC分类号： H01L21/302
CPC分类号： H01L21/02686 , H01L21/02532 , H01L21/02595 , H01L21/2022 , H01L21/2026 , H01L21/268 , H01L29/66757
摘要： A method of fabricating polycrystalline silicon thin film transistor according to the present invention includes: depositing a buffer layer on a substrate; depositing an amorphous silicon layer on the buffer layer with a predetermined thickness; crystallizing the deposited amorphous silicon layer by using a laser to form a polycrystalline silicon layer; etching the crystallized polycrystalline silicon layer to a predetermined thickness; curing the etched polycrystalline silicon layer; and patterning the cured polycrystalline silicon layer to form a semiconductor layer.
摘要翻译：根据本发明的制造多晶硅薄膜晶体管的方法包括：在衬底上沉积缓冲层; 以预定厚度在缓冲层上沉积非晶硅层; 通过使用激光使沉积的非晶硅层结晶以形成多晶硅层; 将结晶的多晶硅层蚀刻至预定厚度; 固化蚀刻的多晶硅层; 以及图案化固化的多晶硅层以形成半导体层。

25. 发明授权

US07215405B2 Dispenser system for liquid crystal display panel and method of using the same 有权
标题翻译：液晶显示面板分配器系统及其使用方法
公开(公告)号：US07215405B2
公开(公告)日：2007-05-08
申请号：US10701489
申请日：2003-11-06
申请人： Sang-Hyun Kim , Sung-Su Jung
发明人： Sang-Hyun Kim , Sung-Su Jung
IPC分类号： G02F1/13 , G02F1/1339
CPC分类号： G02F1/1339
摘要： A dispenser system for a liquid crystal display panel includes a table to overturn a substrate having at least one image display part on a first surface of the overturned substrate, and at least one syringe system to supply sealant onto a first surface of the overturned substrate to form a seal pattern along outer edges of the image display part on the first surface of the overturned substrate, wherein the at least one syringe system moves along horizontal directions.
摘要翻译：一种用于液晶显示面板的分配器系统，包括：在翻转的基板的第一表面上翻转具有至少一个图像显示部分的基板的台，以及至少一个注射器系统，以将密封剂供应到翻转的基板的第一表面上，沿着翻转的基板的第一表面上的图像显示部分的外边缘形成密封图案，其中至少一个注射器系统沿着水平方向移动。

26. 发明申请

US20050095762A1 Mask for crystallizing and method of crystallizing amorphous silicon using the same 有权
标题翻译：用于结晶的掩模和使用其的结晶非晶硅的方法
公开(公告)号：US20050095762A1
公开(公告)日：2005-05-05
申请号：US11004102
申请日：2004-12-06
申请人： Sang-Hyun Kim
发明人： Sang-Hyun Kim
IPC分类号： G02F1/13 , H01L21/20 , H01L21/84
CPC分类号： H01L21/0268 , H01L21/2026
摘要： A method of crystallizing amorphous silicon using a mask having a transmitting portion including a plurality of stripes, wherein end lines of at least two stripes are not collinear; and a blocking portion enclosing the plurality of stripes includes the steps of setting the mask over a substrate having an amorphous silicon layer, applying a first laser beam to a first area of the amorphous silicon layer through the mask, thereby forming a first crystallization region, moving the substrate in a first direction, thereby disposing the blocking portion of the mask over the first crystallization region, and applying a second laser beam to the first area of the amorphous silicon layer through the mask, thereby forming a second crystallization region.
摘要翻译：一种使用具有包括多个条纹的透射部分的掩模使非晶硅结晶的方法，其中至少两条条纹的端行不共线; 并且封闭多个条纹的阻挡部分包括将掩模设置在具有非晶硅层的衬底上的步骤，通过掩模将第一激光束施加到非晶硅层的第一区域，从而形成第一结晶区域，在第一方向移动衬底，从而将掩模的阻挡部分设置在第一结晶区域上，并且通过掩模将第二激光束施加到非晶硅层的第一区域，从而形成第二结晶区域。

27. 发明授权

US06326252B1 Method for fabricating MOS transistor having dual gate 失效
标题翻译：制造具有双栅极的MOS晶体管的方法
公开(公告)号：US06326252B1
公开(公告)日：2001-12-04
申请号：US09481321
申请日：2000-01-11
申请人： Sang Hyun Kim , Nam Hoon Cho , Jae Sung Roh , Jeong Mo Hwang
发明人： Sang Hyun Kim , Nam Hoon Cho , Jae Sung Roh , Jeong Mo Hwang
IPC分类号： H01L218238
CPC分类号： H01L21/76218 , H01L21/823842
摘要： Methods of forming a MOS transistor having dual gates minimizes impurity channeling and diffusion that can occur during impurity injection and activating processes. A method of fabricating the transistor includes the steps of forming a first conduction type well and a second conduction type well in a semiconductor substrate having an isolation region and an active region formed therein. Then, a gate oxide film is formed on an entire surface of the substrate, and a polysilicon layer is deposited on the gate oxide film preferably at a temperature of about 660° C. to about 700° C. and a pressure of about 10 to about 300 Torr. Next, portions of the polysilicon layer and the gate oxide film are selectively removed to form a gate electrode on each of the wells. Impurity ions are injected, having a conduction type opposite a conduction type of the corresponding well, into an exposed surface of each of the wells, to form lightly doped impurity regions. Insulating film sidewalls are formed at sides of each of the gates. Then, first conduction type impurity ions are heavily injected into a surface of the exposed first conduction type well and into the gate electrode formed on the first conduction type well. Also, second conduction type impurity ions are heavily injected into a surface of the exposed second conduction type well and into the gate electrode formed on the second conduction type well. Next, a first heat treatment is conducted in an oxygen ambient and a second heat treatment is conducted in a nitrogen ambient, to diffuse the impurities.
摘要翻译：形成具有双栅极的MOS晶体管的方法使杂质注入和激活过程中可能发生的杂质沟道和扩散最小化。制造晶体管的方法包括以下步骤：在其中形成有隔离区域和有源区域的半导体衬底中形成第一导电类型阱和第二导电类型阱。然后，在基板的整个表面上形成栅极氧化膜，优选在约660℃〜约700℃的温度和约10〜10℃的压力下，在栅极氧化膜上沉积多晶硅层约300乇。接下来，选择性地去除多晶硅层和栅极氧化物膜的部分以在每个阱上形成栅电极。将具有与相应的阱的导电类型相反的导电类型的杂质离子注入每个阱的暴露表面，以形成轻掺杂杂质区。绝缘膜侧壁形成在每个栅极的侧面。然后，第一导电型杂质离子被重度地注入到暴露的第一导电类型阱的表面中并进入形成在第一导电类型阱上的栅电极中。此外，第二导电型杂质离子被严重地注入到暴露的第二导电类型阱的表面中并进入形成在第二导电类型阱上的栅电极中。接下来，在氧环境中进行第一热处理，并且在氮气环境中进行第二热处理以扩散杂质。

28. 发明授权

US09475986B2 Red phosphor and light-emitting device comprising the same 有权
标题翻译：红色荧光体和包含该荧光体的发光装置
公开(公告)号：US09475986B2
公开(公告)日：2016-10-25
申请号：US14118336
申请日：2012-05-18
申请人： Do-Hwan Kim , Sang-Hyun Kim , Chul-Soo Yoon
发明人： Do-Hwan Kim , Sang-Hyun Kim , Chul-Soo Yoon
IPC分类号： C09K11/64 , H01L33/00 , C09K11/77 , C09K11/08 , H05B33/12 , H01L33/50
CPC分类号： C09K11/7728 , C09K11/0883 , C09K11/7734 , C09K11/7739 , H01L33/502 , H01L2224/48247 , H01L2224/48257 , H01L2924/181 , H05B33/12 , H01L2924/00012
摘要： There is provided a red phosphor including a compound represented by an empirical formula Az(Sr,M)2(Si,Al)O4-xNy:R(0
摘要翻译：提供红色荧光体，其包含由经验式Az（Sr，M）2（Si，Al）O 4-x N y：R（0

29. 发明申请

US20140032638A1 AUTOMATED TESTING ENVIRONMENT 有权
标题翻译：自动测试环境
公开(公告)号：US20140032638A1
公开(公告)日：2014-01-30
申请号：US13557653
申请日：2012-07-25
申请人： San Sun PARK , Sang Deuk SHIM , Yoon Hee SHIN , Eun Young CHOI , Sang Hyun KIM
发明人： San Sun PARK , Sang Deuk SHIM , Yoon Hee SHIN , Eun Young CHOI , Sang Hyun KIM
IPC分类号： H04L29/06
CPC分类号： H04L67/42 , G09B7/02 , H04L29/06 , H04L41/5096 , H04L43/0811 , H04L43/50
摘要： Embodiments of this invention are directed to providing an approach that provides an Internet-based testing environment. In a typical embodiment, there is a cloud connect agent that executes while a test-taker is taking a test on a client device. The cloud connect agent is configured to monitor and control certain components of the client device.
摘要翻译：本发明的实施例旨在提供一种提供基于因特网的测试环境的方法。在典型的实施例中，在测试者正在对客户端设备进行测试时，有一个云连接代理执行。云连接代理被配置为监视和控制客户端设备的某些组件。

30. 发明申请

US20120330594A1 METHOD AND APPARATUS FOR ESTIMATING 3D POSITION AND ORIENTATION THROUGH SENSOR FUSION 有权
标题翻译：通过传感器融合估算3D位置和方位的方法和装置
公开(公告)号：US20120330594A1
公开(公告)日：2012-12-27
申请号：US13465428
申请日：2012-05-07
申请人： Hyong Euk LEE , Sang Hyun KIM , Won Chul Bang , Chang Kyu CHOI
发明人： Hyong Euk LEE , Sang Hyun KIM , Won Chul Bang , Chang Kyu CHOI
IPC分类号： G06F15/00
CPC分类号： G01S5/163 , G01S5/16
摘要： An apparatus and method for estimating a three-dimensional (3D) position and orientation based on a sensor fusion process is provided. The method of estimating the 3D position and orientation may include estimating a strength-based position and a strength-based orientation of a remote apparatus when a plurality of strength information is received, based on an attenuation characteristic of a strength that varies based on a distance and orientation, estimating an inertia-based position and an inertia-based orientation of the remote apparatus by receiving a plurality of inertial information, and estimating a fused position based on a weighted-sum of the strength-based position and the inertia-based position, and to estimate a fused orientation based on a weighted-sum of the strength-based orientation and the inertia-based orientation. The strength-based position and the strength-based orientation may be estimated based on a plurality of adjusted strength information from which noise is removed using a plurality of previous strength information.
摘要翻译：提供了一种用于基于传感器融合处理来估计三维（3D）位置和取向的装置和方法。估计3D位置和取向的方法可以包括基于基于距离变化的强度的衰减特性来估计接收到多个强度信息时的远程装置的基于强度的位置和基于强度的取向和取向，通过接收多个惯性信息来估计远程装置的基于惯量的位置和基于惯量的取向，并且基于基于强度的位置和基于惯量的位置的加权和来估计融合位置并且基于基于强度的取向和基于惯性的取向的加权和来估计融合取向。基于强度的位置和基于强度的取向可以基于使用多个先前的强度信息从其中去除噪声的多个调整的强度信息来估计。

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