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21. 发明授权

US06579732B2 Method and apparatus for controlling material removal from a semiconductor substrate using induced current endpointing 有权
公开(公告)号：US06579732B2
公开(公告)日：2003-06-17
申请号：US10027368
申请日：2001-12-20
申请人： Richard H. Livengood , Paul Winer , Gary Woods , Michael DiBattista
发明人： Richard H. Livengood , Paul Winer , Gary Woods , Michael DiBattista
IPC分类号： H01L2166
CPC分类号： H01L21/67253 , H01L22/12 , H01L22/26
摘要： A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.

22. 发明授权

US06525922B2 High performance via capacitor and method for manufacturing same 有权
公开(公告)号：US06525922B2
公开(公告)日：2003-02-25
申请号：US09751358
申请日：2000-12-29
申请人： Paul Winer , Richard H. Livengood , Suresh Ramalingam
发明人： Paul Winer , Richard H. Livengood , Suresh Ramalingam
IPC分类号： H01G4228
CPC分类号： H01L23/49822 , H01L21/563 , H01L23/49827 , H01L23/642 , H01L28/90 , H01L2224/16 , H01L2224/16268 , H01L2224/73203 , H01L2224/73204 , H01L2924/00014 , H01L2924/01057 , H01L2924/01077 , H01L2924/01078 , H01L2924/09701 , H01L2924/10253 , H01L2924/12044 , H01L2924/15311 , H01L2924/00 , H01L2224/0401
摘要： A capacitor structure is formed on a substrate member having one or more via holes therein. Metallization portions within the via holes of the substrate member form part of the plates of the capacitor.

23. 发明授权

US6159753A Method and apparatus for editing an integrated circuit 失效
标题翻译：用于编辑集成电路的方法和装置
公开(公告)号：US6159753A
公开(公告)日：2000-12-12
申请号：US771273
申请日：1996-12-20
申请人： Paul Winer , Richard H. Livengood
发明人： Paul Winer , Richard H. Livengood
IPC分类号： H01L21/00 , H01L21/302 , H01L21/44
CPC分类号： H01L21/28562 , H01L21/76838 , H01L21/76892
摘要： A method and an apparatus for editing an integrated circuit. In one embodiment, an integrated circuit substrate is placed into a laser chemical vapor deposition (LCVD) tool and a conductive metal film is deposited onto the integrated circuit substrate over an area of interest. The integrated circuit substrate is subsequently placed into a focused ion beam (FIB) tool where an optional FIB cleaning step is performed on the conductive element deposited by the LCVD tool to help ensure that a good electrical contact can be made. The FIB tool is also used to introduce any desired cuts into signal lines of the integrated circuit to complete edits. The FIB is also used to remove passivation over integrated circuit nodes of interest to expose buried metal lines for subsequent coupling to the conductive element deposited with the LCVD tool. The FIB tool is then used to deposit a focused ion beam chemical vapor deposition (FIBCVD) conductive element between the exposed integrated circuit nodes of interest and the conductive element deposited with the LCVD tool. As a result, a new conductive element between the nodes of interest is formed through the conductive elements formed by both the LCVD and FIB tools.
摘要翻译：一种用于编辑集成电路的方法和装置。在一个实施例中，将集成电路基板放置在激光化学气相沉积（LCVD）工具中，并且在感兴趣的区域上将导电金属膜沉积到集成电路基板上。集成电路基板随后被放置到聚焦离子束（FIB）工具中，其中在由LCVD工具沉积的导电元件上执行可选的FIB清洁步骤，以帮助确保可以进行良好的电接触。 FIB工具还用于将任何所需的切割引入集成电路的信号线，以完成编辑。 FIB还用于去除感兴趣的集成电路节点上的钝化，以暴露埋入的金属线，以便随后与沉积在LCVD工具上的导电元件耦合。然后，FIB工具用于在所暴露的感兴趣的集成电路节点和沉积有LCVD工具的导电元件之间沉积聚焦离子束化学气相沉积（FIBCVD）导电元件。结果，通过由LCVD和FIB工具形成的导电元件形成感兴趣的节点之间的新的导电元件。

24. 发明授权

US6020746A Method and apparatus for probing an integrated circuit through the back side of an integrated circuit die 失效
标题翻译：用于通过集成电路管芯的背面探测集成电路的方法和装置
公开(公告)号：US6020746A
公开(公告)日：2000-02-01
申请号：US941888
申请日：1997-09-30
申请人： Richard H. Livengood
发明人： Richard H. Livengood
IPC分类号： G01R1/06 , G01R31/28 , G01R31/302 , G01R31/303 , G01R31/3185 , H01J37/305 , H01L21/66 , H01L21/822 , H01L23/544 , H01L27/04
CPC分类号： B24B37/013 , G01R31/2884 , G01R31/318505 , H01J37/3056 , H01L22/26 , H01L23/544 , G01R31/2886 , G01R31/303 , H01J2237/30466 , H01L2223/54473 , H01L2224/16 , H01L2224/48091 , H01L24/48 , H01L2924/00014 , H01L2924/00015 , H01L2924/01039 , H01L2924/01057 , H01L2924/12042 , H01L2924/14 , H01L2924/15312 , H01L2924/1532 , H01L2924/19041 , H01L2924/30107
摘要： A method and an apparatus for probing signals from an integrated circuit through the back side of an integrated circuit die. In one embodiment, a passive diffusion is disposed in a semiconductor substrate of a flip-chip mounted integrated circuit die. The passive diffusion is coupled to a signal line through a contact. The signal line carries the integrated circuit signal of interest. In one embodiment, the disclosed passive diffusion is oversized to reduce attenuation of a signal acquired from the passive diffusion. In addition, the disclosed passive diffusion is laterally spaced from nearby diffusions in the semiconductor substrate of the integrated circuit to enable exposure of the passive diffusion with a reduced risk of damaging nearby structures in the integrated circuit die, such as for example other diffusions, during the exposing process. Moreover, the disclosed passive diffusion is laterally spaced from nearby diffusions to reduce crosstalk interference from the nearby diffusions.
摘要翻译：一种用于从集成电路通过集成电路管芯的背面探测信号的方法和装置。在一个实施例中，无源扩散设置在倒装芯片安装集成电路管芯的半导体衬底中。被动扩散通过触点耦合到信号线。信号线承载感兴趣的集成电路信号。在一个实施例中，所公开的被动扩散被超大以减少从被动扩散获得的信号的衰减。此外，所公开的被动扩散与集成电路的半导体衬底中的附近的扩散横向间隔开，以使被动扩散的曝光降低了集成电路管芯中的附近结构的损害风险，例如其他扩散，曝光过程。此外，所公开的被动扩散与附近的扩散横向间隔开，以减少来自附近扩散的串扰干扰。

25. 发明授权

US6001703A Method of forming a fiducial for aligning an integrated circuit die 失效
标题翻译：形成用于对准集成电路管芯的基准的方法
公开(公告)号：US6001703A
公开(公告)日：1999-12-14
申请号：US978535
申请日：1997-11-26
申请人： Paul Winer , Richard H. Livengood
发明人： Paul Winer , Richard H. Livengood
IPC分类号： H01L23/544 , H01L21/76
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54473 , H01L2223/5448 , H01L2924/0002 , Y10S148/102 , Y10S438/975
摘要： A fiducial for aligning an integrated circuit die. In one embodiment, the fiducial is configured to be exposed by laser chemical etching through a silicon substrate through the back side of a C4 packaged integrated circuit die. The presently described fiducial includes floating diffusion regions disposed in the substrate. An oxide layer free of metal contacts is disposed over the diffusion regions within the fiducial region of the integrated circuit. A metal pattern layer is disposed beneath the oxide layer to provide alignment information. The metal pattern layer is configured to be visible through the oxide layer after the silicon substrate has been removed from the fiducial region. A light block is disposed between the metal pattern layer and an underlying epoxy underfill layer to minimize the risk of an excessive amount of light from being exposed to the underlying epoxy layer, which minimizes the risk of the epoxy layer from damaging the integrated circuit from excessive light exposure. Since the presently described fiducial does not include any contacts in the oxide layer, the additional step of utilizing a focus ion beam mills no longer necessary and the presently described fiducial therefore only needs to be etched with a laser chemical etcher to be exposed.
摘要翻译：用于对准集成电路管芯的基准。在一个实施例中，基准被配置为通过激光化学蚀刻通过硅衬底通过C4封装的集成电路管芯的背面暴露。目前描述的基准包括设置在基板中的浮动扩散区域。没有金属触点的氧化物层设置在集成电路的基准区域内的扩散区域上。金属图案层设置在氧化物层下方以提供对准信息。在从基准区域移除硅衬底之后，金属图案层被配置为通过氧化物层可见。光块被布置在金属图案层和下面的环氧底层填充层之间以最小化暴露于下面的环氧树脂层的过量光的风险，这使得环氧树脂层不会损害集成电路的风险过大曝光由于目前描述的基准点不包括氧化物层中的任何接触，所以利用不再需要的聚焦离子束研磨机的附加步骤因此仅需要用激光化学蚀刻器进行蚀刻来暴露出目前描述的基准。

26. 发明授权

US5948217A Method and apparatus for endpointing while milling an integrated circuit 失效
标题翻译：用于在铣削集成电路时终点的方法和装置
公开(公告)号：US5948217A
公开(公告)日：1999-09-07
申请号：US771712
申请日：1996-12-20
申请人： Paul Winer , Richard H. Livengood
发明人： Paul Winer , Richard H. Livengood
IPC分类号： H01J37/305 , H01L21/66 , C23C14/46 , C23C14/34
CPC分类号： B24B37/013 , H01J37/3056 , H01L22/26 , H01J2237/30466 , H01L2223/54473
摘要： A method and an apparatus for endpoint determination when milling an integrated circuit disposed in a substrate. In one embodiment, the substrate is charged to a first polarity while the well regions and active diffusion regions of the integrated circuit are charged to another polarity thus resulting in an electrical bias at the P-N junctions in the substrate. By powering up the integrated circuit in this fashion during milling, endpoint detection can be accurately determined by using a voltage contrast mechanism such as the imaging detector of a focused ion beam (FIB) milling tool. A diffusion boundary can also be determined in accordance with the teachings of the invention by the use of the stage current monitor of the FIB milling tool. The diffusion boundary is determined in accordance with the teachings of the present invention by a change in contrast as detected by the imaging detector of the FIB milling tool or by a change in the stage current as measured by the stage current monitor of the FIB milling tool. By accurately determining when a diffusion boundary is reached, the present invention reduces the risk of inadvertently destroying diffusion regions when exposing features in an integrated circuit during debug.
摘要翻译：一种用于在铣削设置在基板中的集成电路时终端确定的方法和装置。在一个实施例中，将衬底充电至第一极性，同时将集成电路的阱区和有源扩散区充电至另一极性，从而导致衬底中P-N结的电偏压。通过在铣削期间以这种方式加电集成电路，可以通过使用诸如聚焦离子束（FIB）铣削工具的成像检测器的电压对比机构来精确地确定端点检测。扩散边界也可以根据本发明的教导通过使用FIB铣削工具的级电流监视器来确定。扩散边界根据本发明的教导通过FIB铣刀的成像检测器检测到的对比度变化或通过FIB铣刀的级电流监测器测量的级电流的变化来确定。通过精确地确定何时达到扩散边界，本发明降低了在调试期间暴露集成电路中的特征时无意中破坏扩散区的风险。

27. 发明授权

US5942805A Fiducial for aligning an integrated circuit die 失效
标题翻译：用于对准集成电路管芯的基准
公开(公告)号：US5942805A
公开(公告)日：1999-08-24
申请号：US771275
申请日：1996-12-20
申请人： Paul Winer , Richard H. Livengood
发明人： Paul Winer , Richard H. Livengood
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54473 , H01L2223/5448 , H01L2924/0002 , Y10S148/102 , Y10S438/975
摘要： A fiducial for aligning an integrated circuit die. In one embodiment, the fiducial is configured to be exposed by laser chemical etching through a silicon substrate through the back side of a C4 packaged integrated circuit die. The presently described fiducial includes floating diffusion regions disposed in the substrate. An oxide layer free of metal contacts is disposed over the diffusion regions within the fiducial region of the integrated circuit. A metal pattern layer is disposed beneath the oxide layer to provide alignment information. The metal pattern layer is configured to be visible through the oxide layer after the silicon substrate has been removed from the fiducial region. A light block is disposed between the metal pattern layer and an underlying epoxy underfill layer to minimize the risk of an excessive amount of light from being exposed to the underlying epoxy layer, which minimizes the risk of the epoxy layer from damaging the integrated circuit from excessive light exposure. Since the presently described fiducial does not include any contacts in the oxide layer, the additional step of utilizing a focus ion beam mill is no longer necessary and the presently described fiducial therefore only needs to be etched with a laser chemical etcher to be exposed.
摘要翻译：用于对准集成电路管芯的基准。在一个实施例中，基准被配置为通过激光化学蚀刻通过硅衬底通过C4封装的集成电路管芯的背面暴露。目前描述的基准包括设置在基板中的浮动扩散区域。没有金属触点的氧化物层设置在集成电路的基准区域内的扩散区域上。金属图案层设置在氧化物层下方以提供对准信息。在从基准区域移除硅衬底之后，金属图案层被配置为通过氧化物层可见。光块被布置在金属图案层和下面的环氧底层填充层之间以最小化暴露于下面的环氧树脂层的过量光的风险，这使得环氧树脂层不会损害集成电路的风险过大曝光由于目前描述的基准不包括氧化物层中的任何接触，所以不再需要利用聚焦离子束研磨机的附加步骤，因此目前描述的基准仅需要用激光化学蚀刻剂进行蚀刻来暴露。

28. 发明授权

US5805421A Semiconductor substrate having alignment marks for locating circuitry on the substrate 失效
标题翻译：半导体衬底具有用于在衬底上定位电路的对准标记
公开(公告)号：US5805421A
公开(公告)日：1998-09-08
申请号：US828279
申请日：1997-03-21
申请人： Richard H. Livengood , Paul Winer , Valluri R. Rao
发明人： Richard H. Livengood , Paul Winer , Valluri R. Rao
IPC分类号： H01L23/544 , H05K1/14
CPC分类号： B24B37/013 , H01L23/544 , H01L2223/5442 , H01L2223/54473 , H01L2223/5448 , H01L2224/16 , H01L2224/48091 , H01L24/48 , H01L2924/00014 , H01L2924/00015 , H01L2924/01039 , H01L2924/12042 , H01L2924/14 , H01L2924/15312 , H01L2924/1532 , H01L2924/19041 , H01L2924/30107 , H01L2924/3025
摘要： An integrated circuit device having alignment marks that are located on the integrated circuit device semiconductor substrate and aligned to the integrated circuit. The alignment marks are used in conjunction with a circuit diagram of the integrated circuit to determine the point on the bottom of the semiconductor substrate residing beneath the portion of the integrated circuit which the practitioner desires to access.
摘要翻译：一种集成电路器件，具有位于集成电路器件半导体衬底上并与集成电路对准的对准标记。对准标记与集成电路的电路图一起使用，以确定位于集成电路的部分下面的半导体衬底的底部上的点，从业者希望访问。

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