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21. 发明授权

US07989886B2 Alignment of trench for MOS 有权
标题翻译： MOS沟槽对准
公开(公告)号：US07989886B2
公开(公告)日：2011-08-02
申请号：US12560025
申请日：2009-09-15
申请人： Peter Moens , Marnix Tack
发明人： Peter Moens , Marnix Tack
IPC分类号： H01L29/49
CPC分类号： H01L29/7802 , H01L29/407 , H01L29/41741 , H01L29/66727 , H01L29/7809
摘要： Manufacturing a power transistor by forming a gate structure on a first layer, forming a trench in the first layer, self aligned with the gate structure, and forming part of the transistor in the trench. By forming a spacer next to the gate, the spacer and gate can be used as a mask when forming the trench, to allow space for a source region next to the gate. The self-aligning rather than forming the gate after the trench means the alignment is more accurate, allowing size reduction. Another aspect involves forming a trench in a first layer, filling the trench, forming a second layer on either side of the trench with lateral overgrowth over the trench, and forming a source region in the second layer to overlap the trench. This overlap can enable the chip area to be reduced.
摘要翻译：通过在第一层上形成栅极结构来制造功率晶体管，在第一层中形成沟槽，与栅极结构自对准，并在沟槽中形成晶体管的一部分。通过在栅极附近形成间隔物，当形成沟槽时，间隔物和栅极可用作掩模，以允许邻近栅极的源极区域的空间。自对准而不是在沟槽后形成栅极意味着对准更准确，允许尺寸减小。另一方面涉及在第一层中形成沟槽，填充沟槽，在沟槽的任一侧上形成第二层，在沟槽上具有横向过度生长，以及在第二层中形成与沟槽重叠的源极区。这种重叠可以使芯片面积减小。

22. 发明授权

US07804670B2 Hybrid ESD clamp 有权
标题翻译：混合ESD钳位
公开(公告)号：US07804670B2
公开(公告)日：2010-09-28
申请号：US11794472
申请日：2005-01-07
申请人： Koen Reynders , Peter Moens
发明人： Koen Reynders , Peter Moens
IPC分类号： H02H3/22
CPC分类号： H01L29/7809 , H01L27/0266 , H01L29/1095 , H01L29/7803
摘要： A circuit for protecting a semiconductor from electrostatic discharge events includes a Zener diode (21) in series with a resistor (22) between a power line HV VDD and a ground fine HV VSS. A gate of a DMOS device (23) is connected to a node between the diode and the resistor. The drain and source of the DMOS are connected between the power lines. During an ESD event, the gate voltage of the DMOS increases and the ESD current will be discharged through the DMOS to ground. When the current exceeds the capacity of the channel of the DMOS, a parasitic bipolar transistor or transistors associated with the DMOS device acts in a controlled snapback to discharge the current to ground. The use of a vertical DMOS (VDMOS) instead of a lateral DMOS (LDMOS), can reduce the area of the device and improve the protection.
摘要翻译：用于保护半导体免受静电放电事件的电路包括与电源线HV VDD和接地精细HV VSS之间的电阻器（22）串联的齐纳二极管（21）。 DMOS器件（23）的栅极连接到二极管和电阻器之间的节点。 DMOS的漏极和源极连接在电源线之间。在ESD事件期间，DMOS的栅极电压增加，ESD电流将通过DMOS放电到地。当电流超过DMOS通道的容量时，与DMOS器件相关联的寄生双极晶体管或晶体管作用在受控的快速恢复中，以将电流放电到地。使用垂直DMOS（VDMOS）而不是侧向DMOS（LDMOS），可以减少设备的面积并改善保护。

23. 发明授权

US07709889B2 Semiconductor device with improved breakdown properties and manufacturing method thereof 有权
标题翻译：具有改进的击穿特性的半导体器件及其制造方法
公开(公告)号：US07709889B2
公开(公告)日：2010-05-04
申请号：US11828973
申请日：2007-07-26
申请人： Peter Moens , Filip Bauwens , Joris Baele , Marnix Tack
发明人： Peter Moens , Filip Bauwens , Joris Baele , Marnix Tack
IPC分类号： H01L29/00
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/42368 , H01L29/4916 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/66719 , H01L29/66734 , H01L29/7809
摘要： The present invention provides a semiconductor device (20) comprising a trench (5) formed in a semiconductor substrate formed of a stack (4) of layers (1,2,3), a layer (6) of a first, grown dielectric material covering sidewalls and bottom of the trench (5), the layer (6) including one or more notches (13) at the bottom of the trench (5) and one or more spacers (14) formed of a second, deposited dielectric material to fill the one or more notches (13) in the layer (6) formed of the first, grown dielectric material. The semiconductor device (20) according to the present invention shows improved breakdown voltage and on-resistance. The present invention furthermore provides a method for the manufacturing of such semiconductor devices (20).
摘要翻译：本发明提供一种半导体器件（20），其包括形成在由层（1,2,3）的叠层（4）形成的半导体衬底中的沟槽（5），第一生长电介质材料的层（6）覆盖所述沟槽（5）的侧壁和底部，所述层（6）在所述沟槽（5）的底部包括一个或多个凹口（13）以及一个或多个由第二沉积介电材料形成的间隔物（14）填充由第一种生长的电介质材料形成的层（6）中的一个或多个凹口（13）。根据本发明的半导体器件（20）显示出改进的击穿电压和导通电阻。本发明还提供了制造这种半导体器件（20）的方法。

24. 发明申请

US20100065908A1 ALIGNMENT OF TRENCH FOR MOS 有权
标题翻译： MOS的对准
公开(公告)号：US20100065908A1
公开(公告)日：2010-03-18
申请号：US12560025
申请日：2009-09-15
申请人： Peter MOENS , Marnix Tack
发明人： Peter MOENS , Marnix Tack
IPC分类号： H01L27/088
CPC分类号： H01L29/7802 , H01L29/407 , H01L29/41741 , H01L29/66727 , H01L29/7809
摘要： Manufacturing a power transistor by forming a gate structure on a first layer, forming a trench in the first layer, self aligned with the gate structure, and forming part of the transistor in the trench. By forming a spacer next to the gate, the spacer and gate can be used as a mask when forming the trench, to allow space for a source region next to the gate. The self-aligning rather than forming the gate after the trench means the alignment is more accurate, allowing size reduction. Another aspect involves forming a trench in a first layer, filling the trench, forming a second layer on either side of the trench with lateral overgrowth over the trench, and forming a source region in the second layer to overlap the trench. This overlap can enable the chip area to be reduced.
摘要翻译：通过在第一层上形成栅极结构来制造功率晶体管，在第一层中形成沟槽，与栅极结构自对准，并在沟槽中形成晶体管的一部分。通过在栅极附近形成间隔物，当形成沟槽时，间隔物和栅极可用作掩模，以允许邻近栅极的源极区域的空间。自对准而不是在沟槽后形成栅极意味着对准更准确，允许尺寸减小。另一方面涉及在第一层中形成沟槽，填充沟槽，在沟槽的任一侧上形成第二层，在沟槽上具有横向过度生长，以及在第二层中形成与沟槽重叠的源极区。这种重叠可以使芯片面积减小。

25. 发明申请

US20090268357A1 Hybrid ESD Clamp 有权
标题翻译：混合ESD钳位
公开(公告)号：US20090268357A1
公开(公告)日：2009-10-29
申请号：US11794472
申请日：2005-01-07
申请人： Koen Reynders , Peter Moens
发明人： Koen Reynders , Peter Moens
IPC分类号： H02H9/04 , H01L21/8249
CPC分类号： H01L29/7809 , H01L27/0266 , H01L29/1095 , H01L29/7803
摘要： A circuit for protecting a semiconductor from electrostatic discharge events includes a Zener diode (21) in series with a resistor (22) between a power line HV VDD and a ground fine HV VSS. A gate of a DMOS device (23) is connected to a node between the diode and the resistor. The drain and source of the DMOS are connected between the power lines. During an ESD event, the gate voltage of the DMOS increases and the ESD current will be discharged through the DMOS to ground. When the current exceeds the capacity of the channel of the DMOS, a parasitic bipolar transistor or transistors associated with the DMOS device acts in a controlled snapback to discharge the current to ground. The use of a vertical DMOS (VDMOS) instead of a lateral DMOS (LDMOS), can reduce the area of the device and improve the protection.
摘要翻译：用于保护半导体免受静电放电事件的电路包括与电源线HV VDD和接地精细HV VSS之间的电阻器（22）串联的齐纳二极管（21）。 DMOS器件（23）的栅极连接到二极管和电阻器之间的节点。 DMOS的漏极和源极连接在电源线之间。在ESD事件期间，DMOS的栅极电压增加，ESD电流将通过DMOS放电到地。当电流超过DMOS通道的容量时，与DMOS器件相关联的寄生双极晶体管或晶体管作用在受控的快速恢复中，以将电流放电到地。使用垂直DMOS（VDMOS）而不是侧向DMOS（LDMOS），可以减少设备的面积并改善保护。

26. 发明授权

US07608510B2 Alignment of trench for MOS 有权
标题翻译： MOS沟槽对准
公开(公告)号：US07608510B2
公开(公告)日：2009-10-27
申请号：US11408924
申请日：2006-04-24
申请人： Peter Moens , Marnix Tack
发明人： Peter Moens , Marnix Tack
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L29/407 , H01L29/41741 , H01L29/66727 , H01L29/7809
摘要： Manufacturing a power transistor by forming a gate structure on a first layer, forming a trench in the first layer, self aligned with the gate structure, and forming part of the transistor in the trench. By forming a spacer next to the gate, the spacer and gate can be used as a mask when forming the trench, to allow space for a source region next to the gate. The self-aligning rather than forming the gate after the trench means the alignment is more accurate, allowing size reduction. Another aspect involves forming a trench in a first layer, filling the trench, forming a second layer on either side of the trench with lateral overgrowth over the trench, and forming a source region in the second layer to overlap the trench. This overlap can enable the chip area to be reduced.
摘要翻译：通过在第一层上形成栅极结构来制造功率晶体管，在第一层中形成沟槽，与栅极结构自对准，并在沟槽中形成晶体管的一部分。通过在栅极附近形成间隔物，当形成沟槽时，间隔物和栅极可用作掩模，以允许邻近栅极的源极区域的空间。自对准而不是在沟槽后形成栅极意味着对准更准确，允许尺寸减小。另一方面涉及在第一层中形成沟槽，填充沟槽，在沟槽的任一侧上形成第二层，在沟槽上具有横向过度生长，以及在第二层中形成与沟槽重叠的源极区。这种重叠可以使芯片面积减小。

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