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1. 发明授权

US08648398B2 Electronic device and a transistor including a trench and a sidewall doped region 有权
标题翻译：电子器件和包括沟槽和侧壁掺杂区域的晶体管
公开(公告)号：US08648398B2
公开(公告)日：2014-02-11
申请号：US13627287
申请日：2012-09-26
申请人： Jaume Roig-Guitart , Peter Moens , Marnix Tack
发明人： Jaume Roig-Guitart , Peter Moens , Marnix Tack
IPC分类号： H01L29/78
CPC分类号： H01L29/41766 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/41741 , H01L29/456 , H01L29/66719 , H01L29/7809
摘要： An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.
摘要翻译：电子器件可以包括具有主表面的第一层，与主表面相邻的阱区，以及与主表面和阱区间隔开的掩埋掺杂区。电子器件还可以包括朝向掩埋掺杂区域延伸的沟槽，其中沟槽具有侧壁，以及沿沟槽侧壁的侧壁掺杂区域，其中侧壁掺杂区域延伸到比阱区深的深度。第一层和埋藏区具有第一导电类型，并且阱区具有与第一导电类型相反的第二导电类型。电子器件可以在沟槽内包括导电结构，其中导电结构电连接到掩埋掺杂区并与侧壁掺杂区电绝缘。还描述了用于形成电子设备的过程。

2. 发明申请

US20060249786A1 Alignment of trench for MOS 有权
公开(公告)号：US20060249786A1
公开(公告)日：2006-11-09
申请号：US11408924
申请日：2006-04-24
申请人： Peter Moens , Marnix Tack
发明人： Peter Moens , Marnix Tack
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L29/7802 , H01L29/407 , H01L29/41741 , H01L29/66727 , H01L29/7809
摘要： Manufacturing a power transistor by forming a gate structure on a first layer, forming a trench in the first layer, self aligned with the gate structure, and forming part of the transistor in the trench. By forming a spacer next to the gate, the spacer and gate can be used as a mask when forming the trench, to allow space for a source region next to the gate. The self-aligning rather than forming the gate after the trench means the alignment is more accurate, allowing size reduction. Another aspect involves forming a trench in a first layer, filling the trench, forming a second layer on either side of the trench with lateral overgrowth over the trench, and forming a source region in the second layer to overlap the trench. This overlap can enable the chip area to be reduced.

3. 发明申请

US20100105188A1 DOUBLE TRENCH FOR ISOLATION OF SEMICONDUCTOR DEVICES 有权
标题翻译：用于隔离半导体器件的双光栅
公开(公告)号：US20100105188A1
公开(公告)日：2010-04-29
申请号：US12651683
申请日：2010-01-04
申请人： Peter MOENS , Marnix Tack , Sylvie Boonen , Paul Colson
发明人： Peter MOENS , Marnix Tack , Sylvie Boonen , Paul Colson
IPC分类号： H01L21/762
CPC分类号： H01L21/3081 , H01L21/3083 , H01L21/76205 , H01L21/76229
摘要： Semiconductor device has a substrate (50), a buried layer (55), an active area extending from a surface contact to the buried layer, an insulator (130) in a first trench extending towards the buried layer, to isolate the active area, and a second insulator (130) in a second deep trench and extending through the buried layer to isolate the buried layer and the active area from other pails of the substrate. This double trench can help reduce the area needed for the electrical isolation between the active device and the other devices. Such reduction in area can enable greater integration or more cells in a multi cell super-MOS device, and so improve performance parameters such as Ron. The double trench can be manufactured using a first mask to etch both trenches at the same time, and subsequently using a second mask to etch the second deep trench deeper.
摘要翻译：半导体器件具有衬底（50），掩埋层（55），从表面接触延伸到掩埋层的有源区，在朝向掩埋层延伸的第一沟槽中的绝缘体（130），以隔离有源区，以及在第二深沟槽中的第二绝缘体（130），并且延伸穿过所述掩埋层以将所述掩埋层和所述有源区域与所述衬底的其它桶隔离。该双沟槽可以帮助减少有源器件与其他器件之间的电气隔离所需的面积。这样的面积减少可以实现多单元超MOS器件中的更大的集成或更多的单元，并且因此改进诸如Ron的性能参数。可以使用第一掩模制造双沟槽以同时蚀刻两个沟槽，并且随后使用第二掩模来更深地蚀刻第二深沟槽。

4. 发明授权

US07667270B2 Double trench for isolation of semiconductor devices 有权
标题翻译：用于隔离半导体器件的双沟槽
公开(公告)号：US07667270B2
公开(公告)日：2010-02-23
申请号：US11399377
申请日：2006-04-07
申请人： Peter Moens , Marnix Tack , Sylvie Boonen , Paul Colson
发明人： Peter Moens , Marnix Tack , Sylvie Boonen , Paul Colson
IPC分类号： H01L21/331
CPC分类号： H01L21/3081 , H01L21/3083 , H01L21/76205 , H01L21/76229
摘要： A semiconductor device has a substrate (50), a buried layer (55), an active area extending from a surface contact to the buried layer, an insulator (130) in a first trench extending towards the buried layer, to isolate the active area, and a second insulator (130) in a second deep trench and extending through the buried layer to isolate the buried layer and the active area from other parts of the substrate. This double trench can help reduce the area needed for the electrical isolation between the active device and the other devices. Such reduction in area can enable greater integration or more cells in a multi cell super-MOS device, and so improve performance parameters such as Ron. The double trench can be manufactured using a first mask to etch both trenches at the same time, and subsequently using a second mask to etch the second deep trench deeper.
摘要翻译：半导体器件具有衬底（50），掩埋层（55），从表面接触延伸到掩埋层的有源区，在朝向掩埋层延伸的第一沟槽中的绝缘体（130），以隔离有源区，以及第二深沟槽中的第二绝缘体（130），并延伸穿过所述掩埋层以将所述掩埋层和所述有源区域与所述衬底的其它部分隔离。该双沟槽可以帮助减少有源器件与其他器件之间的电气隔离所需的面积。这样的面积减少可以实现多单元超MOS器件中的更大的集成或更多的单元，并且因此改进诸如Ron的性能参数。可以使用第一掩模制造双沟槽以同时蚀刻两个沟槽，并且随后使用第二掩模来更深地蚀刻第二深沟槽。

5. 发明申请

US20060244029A1 Double trench for isolation of semiconductor devices 有权
标题翻译：用于隔离半导体器件的双沟槽
公开(公告)号：US20060244029A1
公开(公告)日：2006-11-02
申请号：US11399377
申请日：2006-04-07
申请人： Peter Moens , Marnix Tack , Sylvie Boonen , Paul Colson
发明人： Peter Moens , Marnix Tack , Sylvie Boonen , Paul Colson
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119 , H01L21/76
CPC分类号： H01L21/3081 , H01L21/3083 , H01L21/76205 , H01L21/76229
摘要： A semiconductor device has a substrate (50), a buried layer (55), an active area extending from a surface contact to the buried layer, an insulator (130) in a first trench extending towards the buried layer, to isolate the active area, and a second insulator (130) in a second deep trench and extending through the buried layer to isolate the buried layer and the active area from other parts of the substrate. This double trench can help reduce the area needed for the electrical isolation between the active device and the other devices. Such reduction in area can enable greater integration or more cells in a multi cell super-MOS device, and so improve performance parameters such as Ron. The double trench can be manufactured using a first mask to etch both trenches at the same time, and subsequently using a second mask to etch the second deep trench deeper.
摘要翻译：半导体器件具有衬底（50），掩埋层（55），从表面接触延伸到掩埋层的有源区，在朝向掩埋层延伸的第一沟槽中的绝缘体（130），以隔离有源区，以及第二深沟槽中的第二绝缘体（130），并延伸穿过所述掩埋层以将所述掩埋层和所述有源区域与所述衬底的其它部分隔离。该双沟槽可以帮助减少有源器件与其他器件之间的电气隔离所需的面积。这样的面积减少可以实现多单元超MOS器件中的更大的集成或更多的单元，并且因此改进诸如Ron的性能参数。可以使用第一掩模制造双沟槽以同时蚀刻两个沟槽，并且随后使用第二掩模来更深地蚀刻第二深沟槽。

6. 发明申请

US20100140698A1 ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN AND A PROCESS OF FORMING THE SAME 有权
标题翻译：电子设备，其中包括一个TRENCH和一个导电结构及其形成过程
公开(公告)号：US20100140698A1
公开(公告)日：2010-06-10
申请号：US12331985
申请日：2008-12-10
申请人： Jaume Roig-Guitart , Peter Moens , Marnix Tack
发明人： Jaume Roig-Guitart , Peter Moens , Marnix Tack
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/41766 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/41741 , H01L29/456 , H01L29/66719 , H01L29/7809
摘要： An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.
摘要翻译：电子器件可以包括具有主表面的第一层，与主表面相邻的阱区，以及与主表面和阱区间隔开的掩埋掺杂区。电子器件还可以包括朝向掩埋掺杂区域延伸的沟槽，其中沟槽具有侧壁，以及沿沟槽侧壁的侧壁掺杂区域，其中侧壁掺杂区域延伸到比阱区深的深度。第一层和埋藏区具有第一导电类型，并且阱区具有与第一导电类型相反的第二导电类型。电子器件可以在沟槽内包括导电结构，其中导电结构电连接到掩埋掺杂区并与侧壁掺杂区电绝缘。还描述了用于形成电子设备的过程。

7. 发明授权

US08298889B2 Process of forming an electronic device including a trench and a conductive structure therein 有权
标题翻译：在其中形成包括沟槽和导电结构的电子器件的工艺
公开(公告)号：US08298889B2
公开(公告)日：2012-10-30
申请号：US12331985
申请日：2008-12-10
申请人： Jaume Roig-Guitart , Peter Moens , Marnix Tack
发明人： Jaume Roig-Guitart , Peter Moens , Marnix Tack
IPC分类号： H01L21/00
CPC分类号： H01L29/41766 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/41741 , H01L29/456 , H01L29/66719 , H01L29/7809
摘要： An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.
摘要翻译：电子器件可以包括具有主表面的第一层，与主表面相邻的阱区，以及与主表面和阱区间隔开的掩埋掺杂区。电子器件还可以包括朝向掩埋掺杂区域延伸的沟槽，其中沟槽具有侧壁，以及沿沟槽侧壁的侧壁掺杂区域，其中侧壁掺杂区域延伸到比阱区深的深度。第一层和埋藏区具有第一导电类型，并且阱区具有与第一导电类型相反的第二导电类型。电子器件可以在沟槽内包括导电结构，其中导电结构电连接到掩埋掺杂区并与侧壁掺杂区电绝缘。还描述了用于形成电子设备的过程。

8. 发明授权

US07989886B2 Alignment of trench for MOS 有权
标题翻译： MOS沟槽对准
公开(公告)号：US07989886B2
公开(公告)日：2011-08-02
申请号：US12560025
申请日：2009-09-15
申请人： Peter Moens , Marnix Tack
发明人： Peter Moens , Marnix Tack
IPC分类号： H01L29/49
CPC分类号： H01L29/7802 , H01L29/407 , H01L29/41741 , H01L29/66727 , H01L29/7809
摘要： Manufacturing a power transistor by forming a gate structure on a first layer, forming a trench in the first layer, self aligned with the gate structure, and forming part of the transistor in the trench. By forming a spacer next to the gate, the spacer and gate can be used as a mask when forming the trench, to allow space for a source region next to the gate. The self-aligning rather than forming the gate after the trench means the alignment is more accurate, allowing size reduction. Another aspect involves forming a trench in a first layer, filling the trench, forming a second layer on either side of the trench with lateral overgrowth over the trench, and forming a source region in the second layer to overlap the trench. This overlap can enable the chip area to be reduced.
摘要翻译：通过在第一层上形成栅极结构来制造功率晶体管，在第一层中形成沟槽，与栅极结构自对准，并在沟槽中形成晶体管的一部分。通过在栅极附近形成间隔物，当形成沟槽时，间隔物和栅极可用作掩模，以允许邻近栅极的源极区域的空间。自对准而不是在沟槽后形成栅极意味着对准更准确，允许尺寸减小。另一方面涉及在第一层中形成沟槽，填充沟槽，在沟槽的任一侧上形成第二层，在沟槽上具有横向过度生长，以及在第二层中形成与沟槽重叠的源极区。这种重叠可以使芯片面积减小。

9. 发明授权

US07709889B2 Semiconductor device with improved breakdown properties and manufacturing method thereof 有权
标题翻译：具有改进的击穿特性的半导体器件及其制造方法
公开(公告)号：US07709889B2
公开(公告)日：2010-05-04
申请号：US11828973
申请日：2007-07-26
申请人： Peter Moens , Filip Bauwens , Joris Baele , Marnix Tack
发明人： Peter Moens , Filip Bauwens , Joris Baele , Marnix Tack
IPC分类号： H01L29/00
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/42368 , H01L29/4916 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/66719 , H01L29/66734 , H01L29/7809
摘要： The present invention provides a semiconductor device (20) comprising a trench (5) formed in a semiconductor substrate formed of a stack (4) of layers (1,2,3), a layer (6) of a first, grown dielectric material covering sidewalls and bottom of the trench (5), the layer (6) including one or more notches (13) at the bottom of the trench (5) and one or more spacers (14) formed of a second, deposited dielectric material to fill the one or more notches (13) in the layer (6) formed of the first, grown dielectric material. The semiconductor device (20) according to the present invention shows improved breakdown voltage and on-resistance. The present invention furthermore provides a method for the manufacturing of such semiconductor devices (20).
摘要翻译：本发明提供一种半导体器件（20），其包括形成在由层（1,2,3）的叠层（4）形成的半导体衬底中的沟槽（5），第一生长电介质材料的层（6）覆盖所述沟槽（5）的侧壁和底部，所述层（6）在所述沟槽（5）的底部包括一个或多个凹口（13）以及一个或多个由第二沉积介电材料形成的间隔物（14）填充由第一种生长的电介质材料形成的层（6）中的一个或多个凹口（13）。根据本发明的半导体器件（20）显示出改进的击穿电压和导通电阻。本发明还提供了制造这种半导体器件（20）的方法。

10. 发明申请

US20100065908A1 ALIGNMENT OF TRENCH FOR MOS 有权
标题翻译： MOS的对准
公开(公告)号：US20100065908A1
公开(公告)日：2010-03-18
申请号：US12560025
申请日：2009-09-15
申请人： Peter MOENS , Marnix Tack
发明人： Peter MOENS , Marnix Tack
IPC分类号： H01L27/088
CPC分类号： H01L29/7802 , H01L29/407 , H01L29/41741 , H01L29/66727 , H01L29/7809
摘要： Manufacturing a power transistor by forming a gate structure on a first layer, forming a trench in the first layer, self aligned with the gate structure, and forming part of the transistor in the trench. By forming a spacer next to the gate, the spacer and gate can be used as a mask when forming the trench, to allow space for a source region next to the gate. The self-aligning rather than forming the gate after the trench means the alignment is more accurate, allowing size reduction. Another aspect involves forming a trench in a first layer, filling the trench, forming a second layer on either side of the trench with lateral overgrowth over the trench, and forming a source region in the second layer to overlap the trench. This overlap can enable the chip area to be reduced.
摘要翻译：通过在第一层上形成栅极结构来制造功率晶体管，在第一层中形成沟槽，与栅极结构自对准，并在沟槽中形成晶体管的一部分。通过在栅极附近形成间隔物，当形成沟槽时，间隔物和栅极可用作掩模，以允许邻近栅极的源极区域的空间。自对准而不是在沟槽后形成栅极意味着对准更准确，允许尺寸减小。另一方面涉及在第一层中形成沟槽，填充沟槽，在沟槽的任一侧上形成第二层，在沟槽上具有横向过度生长，以及在第二层中形成与沟槽重叠的源极区。这种重叠可以使芯片面积减小。

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