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    • 22. 发明授权
    • Apparatus and method for accelerating initial lock time of delayed locked loop
    • 延迟锁定环的加速初始锁定时间的装置和方法
    • US06445234B1
    • 2002-09-03
    • US09473685
    • 1999-12-29
    • Min-Ho YoonJong-Hee Han
    • Min-Ho YoonJong-Hee Han
    • H03L700
    • G11C7/222G11C7/22H03L7/0814H03L7/087H03L7/10
    • An apparatus and method for accelerating an initial lock time of the DLL in a high rate double data rate (DDR) synchronous random access memory (SDRAM) is disclosed. The apparatus for accelerating an initial lock time of the DLL comprises a first clock generator for generating a reference clock signal based on the external synchronization clock signal; a phase comparator for applying a unit delay time and a multiple unit delay time to the internal clock signal and for comparing phases of the internal clock signal, a unit delayed internal clock signal and a multiple unit delayed internal clock signal with a phase of the reference clock signal; a shift controller for selecting an amount of delay time based on a comparison result; a delay unit for delaying the internal clock signal by the amount of delay time based on a selected amount of delay time; and a delay clock modeling unit for generating a modeled delay clock signal corresponding to a delayed internal clock signal and for providing the modeled delay clock signal with the phase comparator for applying a unit delay and a multiple unit delay time.
    • 公开了一种用于加速DLL在高速双倍数据速率(DDR)同步随机存取存储器(SDRAM)中的初始锁定时间的装置和方法。 用于加速DLL的初始锁定时间的装置包括:第一时钟发生器,用于基于外部同步时钟信号产生参考时钟信号; 相位比较器,用于将单位延迟时间和多个单位延迟时间应用于内部时钟信号,并用于比较内部时钟信号,单位延迟内部时钟信号和多单位延迟内部时钟信号的相位,并具有参考相位 时钟信号; 移位控制器,用于基于比较结果选择延迟时间量; 延迟单元,用于基于所选择的延迟时间量将所述内部时钟信号延迟所述延迟时间量; 以及延迟时钟建模单元,用于产生对应于延迟的内部时钟信号的建模的延迟时钟信号,并且用于向模拟的延迟时钟信号提供相位比较器,用于施加单位延迟和多个单位延迟时间。