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21. 发明授权

US07162609B2 Translation lookaside buffer prediction mechanism 有权
公开(公告)号：US07162609B2
公开(公告)日：2007-01-09
申请号：US10726885
申请日：2003-12-03
申请人： Michael W. Morrow , Dennis M. O'Connor , Desikan Iyadurai
发明人： Michael W. Morrow , Dennis M. O'Connor , Desikan Iyadurai
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/654
摘要： According to one embodiment a central processing unit (CPU) is disclosed. The CPU includes a translation lookaside buffer (TLB). The TLB predicts a set index value prior to the generation of an effective address.

22. 发明授权

US06664775B1 Apparatus having adjustable operational modes and method therefore 有权
标题翻译：因此，具有可调节的操作模式和方法的装置
公开(公告)号：US06664775B1
公开(公告)日：2003-12-16
申请号：US09643082
申请日：2000-08-21
申请人： Lawrence T. Clark , Michael W. Morrow , Gregory B. Tucker , Yuan-Po Ypt Tseng , Ali Minaei , Jay Heeb
发明人： Lawrence T. Clark , Michael W. Morrow , Gregory B. Tucker , Yuan-Po Ypt Tseng , Ali Minaei , Jay Heeb
IPC分类号： H02J312
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator and a clock divider that may be used to adjust the operational frequency and/or voltage potential of the integrated circuit to reduce the power consumption of the integrated circuit while in operation.
摘要翻译：简而言之，根据本发明的一个实施例，集成电路具有电压调节器和时钟分频器，其可用于调整集成电路的工作频率和/或电压电位以降低集成电路的功耗，同时在运行。

23. 发明授权

US06624535B2 Digitally controlling the output voltage of a plurality of voltage sources 有权
公开(公告)号：US06624535B2
公开(公告)日：2003-09-23
申请号：US09785920
申请日：2001-02-17
申请人： Michael W. Morrow
发明人： Michael W. Morrow
IPC分类号： H02J734
CPC分类号： H02J7/0024 , Y10T307/50 , Y10T307/527 , Y10T307/653 , Y10T307/724
摘要： A plurality of the voltage sources may be selectively connectable in a variety of different arrangements using a switch array whose connections are determined by a programmable controller. For example, a desired output voltage may be automatically provided by altering the connections between the voltage sources to achieve the desired voltage. A programmable controller may determine how to connect the voltage sources to achieve the desired output voltage.

24. 发明申请

US20130086359A1 Processor Hardware Pipeline Configured for Single-Instruction Address Extraction and Memory Access Operation 审中-公开
标题翻译：处理器硬件管道配置为单指令地址提取和存储器访问操作
公开(公告)号：US20130086359A1
公开(公告)日：2013-04-04
申请号：US13248329
申请日：2011-09-29
申请人： Subrato K. De , Michael W. Morrow , Moinul H. Khan , Mark Bapst
发明人： Subrato K. De , Michael W. Morrow , Moinul H. Khan , Mark Bapst
IPC分类号： G06F12/00 , G06F9/30
CPC分类号： G06F9/30043
摘要： Memory access instructions, such as load and store instructions, are processed in a processor-based system. Processor hardware pipeline configurations enable efficient performance of memory access instructions, such as a pipeline configuration that enables, for a memory access operation request by a register-operand based virtual machine, computation of the memory location corresponding to a virtual-machine register by extracting a bit-field from the virtual-machine instruction and accessing (load or store) the computed memory location that represents a virtual register of the virtual-machine, in a single pass through the pipeline. Thus this processor hardware pipeline configuration enables a virtual machine register read/write operation to be performed by a single hardware processor instruction through a single pass in the processor hardware pipeline, for a register-operand based virtual machine.
摘要翻译：诸如加载和存储指令之类的存储器访问指令在基于处理器的系统中被处理。处理器硬件流水线配置能够有效地执行存储器访问指令，例如流水线配置，其能够通过基于寄存器操作数的虚拟机对存储器访问操作请求进行与虚拟机寄存器对应的存储器位置的计算，来自虚拟机指令的位字段，并且在通过管道的单次通过中访问（加载或存储）表示虚拟机的虚拟寄存器的计算的存储器位置。因此，这种处理器硬件流水线配置使得能够通过单个硬件处理器指令通过处理器硬件流水线中的单次执行对基于寄存器操作数的虚拟机执行虚拟机寄存器读/写操作。

25. 发明授权

US07987337B1 Translation lookaside buffer prediction mechanism 有权
标题翻译：翻译后备缓冲区预测机制
公开(公告)号：US07987337B1
公开(公告)日：2011-07-26
申请号：US12286360
申请日：2008-09-30
申请人： Michael W. Morrow , Dennis M. O'Connor , Desikan Iyadurai
发明人： Michael W. Morrow , Dennis M. O'Connor , Desikan Iyadurai
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/654
摘要： A memory management unit includes a translation lookaside buffer including a page table. The page table includes M entries where M is an integer greater than zero. A register interface selects one of the M entries. The translation lookaside buffer calculates an effective address based on the selected one of the M entries while at least one of mapping the selected one of the M entries to an index and selecting a set of the M entries based on a control signal.
摘要翻译：存储器管理单元包括包括页表的翻译后备缓冲器。页表包括M个条目，其中M是大于零的整数。寄存器接口选择M个条目之一。翻译后备缓冲器基于M个条目中选择的一个计算有效地址，而至少一个将M个条目中选择的一个映射到索引，并且基于控制信号选择一组M个条目。

26. 发明申请

US20100211744A1 METHODS AND APARATUS FOR LOW INTRUSION SNOOP INVALIDATION 有权
标题翻译：低侵入性SNOOP无效的方法和方法
公开(公告)号：US20100211744A1
公开(公告)日：2010-08-19
申请号：US12388545
申请日：2009-02-19
申请人： Michael W. Morrow , James Norris Dieffenderfer
发明人： Michael W. Morrow , James Norris Dieffenderfer
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0831 , G06F12/0808 , Y02D10/13
摘要： Efficient techniques are described for tracking a potential invalidation of a data cache entry in a data cache for which coherency is required. Coherency information is received that indicates a potential invalidation of a data cache entry. The coherency information in association with the data cache entry is retained to track the potential invalidation to the data cache entry. The retained coherency information is kept separate from state bits that are utilized in cache access operations. An invalidate bit, associated with a data cache entry, may be utilized to represents a potential invalidation of the data cache entry. The invalidate bit is set in response to the coherency information, to track the potential invalidation of the data cache entry. A valid bit associated with the data cache entry is set in response to the active invalidate bit and a memory synchronization command. The set invalidate bit is cleared after the valid bit has been cleared.
摘要翻译：描述了用于跟踪需要一致性的数据高速缓存中的数据高速缓存条目的潜在无效的高效技术。一致性信息被接收，指示数据高速缓存条目的潜在无效。与数据高速缓存条目相关联的一致性信息被保留以跟踪对数据高速缓存条目的潜在无效。保留的一致性信息与在缓存访问操作中使用的状态位分开。与数据高速缓存条目相关联的无效位可用于表示数据高速缓存条目的潜在无效。响应于一致性信息设置无效位以跟踪数据高速缓存条目的潜在无效。响应于活动无效位和存储器同步命令来设置与数据高速缓存条目相关联的有效位。置位无效位在有效位清零后清零。

27. 发明授权

US07437512B2 Low power semi-trace instruction/trace hybrid cache with logic for indexing the trace cache under certain conditions 有权
标题翻译：低功耗半跟踪指令/跟踪混合高速缓存，具有用于在特定条件下对跟踪缓存进行索引的逻辑
公开(公告)号：US07437512B2
公开(公告)日：2008-10-14
申请号：US10788725
申请日：2004-02-26
申请人： Michael W. Morrow
发明人： Michael W. Morrow
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F9/3808 , G06F9/3802 , G06F9/3814 , G06F12/0875
摘要： A semi-trace cache combines elements and features of an instruction cache and a trace cache. An ICache portion of the semi-trace cache is filled with instructions fetched from the next level of the memory hierarchy while a TCache portion is filled with traces gleaned either from the actual stream of retired instructions or predicted before execution.
摘要翻译：半跟踪缓存组合指令高速缓存和跟踪高速缓存的元素和特征。半跟踪缓存的ICache部分填充有从内存层次结构的下一级获取的指令，而TCache部分填充了从实际的退出指令流或执行之前预测的跟踪。

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