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21. 发明授权

US08107293B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08107293B2
公开(公告)日：2012-01-31
申请号：US13004926
申请日：2011-01-12
申请人： Masahiro Yoshihara , Toshiaki Edahiro , Koji Hosono
发明人： Masahiro Yoshihara , Toshiaki Edahiro , Koji Hosono
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C7/065 , G11C7/067 , G11C16/24 , G11C16/26 , G11C2207/063 , G11C2207/068
摘要： A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes.
摘要翻译：半导体存储器件包括连接到位线的多个存储器单元; 以及读出放大器，用于感测在连接到位线的所选择的存储器单元中经由位线流动的单元电流的大小，以确定存储在存储单元中的数据的值。感测放大器包括用于预充电的第一晶体管，用于经由第一和第二感测节点在位线中提供电流，插入在第一和第二感测节点之间的用于电荷转移的第二晶体管和用于连续电流供应的第三晶体管以不通过第一和第二感测节点在位线中提供电流。

22. 发明授权

US07881120B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07881120B2
公开(公告)日：2011-02-01
申请号：US12408260
申请日：2009-03-20
申请人： Masahiro Yoshihara , Toshiaki Edahiro , Koji Hosono
发明人： Masahiro Yoshihara , Toshiaki Edahiro , Koji Hosono
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C7/065 , G11C7/067 , G11C16/24 , G11C16/26 , G11C2207/063 , G11C2207/068
摘要： A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes.
摘要翻译：半导体存储器件包括连接到位线的多个存储器单元; 以及读出放大器，用于感测在连接到位线的所选择的存储器单元中经由位线流动的单元电流的大小，以确定存储在存储单元中的数据的值。感测放大器包括用于预充电的第一晶体管，用于经由第一和第二感测节点在位线中提供电流，插入在第一和第二感测节点之间的用于电荷转移的第二晶体管和用于连续电流供应的第三晶体管以不通过第一和第二感测节点在位线中提供电流。

23. 发明授权

US06985023B2 Selective switching of a transistor's back gate potential 失效
标题翻译：选择性切换晶体管的背栅电位
公开(公告)号：US06985023B2
公开(公告)日：2006-01-10
申请号：US10768394
申请日：2004-01-30
申请人： Mami Kawabata , Masahiro Yoshihara , Eiichi Makino
发明人： Mami Kawabata , Masahiro Yoshihara , Eiichi Makino
IPC分类号： H03K19/0185 , H03K17/687
CPC分类号： G05F1/56 , G11C5/147 , H01L27/105
摘要： A semiconductor device comprises a first transistor and a potential generator circuit. The first transistor has a first conduction type first semiconductor region and a second conduction type second semiconductor region formed in the first semiconductor region. The first and second semiconductor regions are supplied with first and second prescribed potentials, respectively. The potential generator circuit generates the first prescribed potential. The potential generator circuit has a first power supply terminal supplied with a first power supply potential, a second power supply terminal supplied with a second power supply potential set to a higher potential than the first power supply potential, and an output terminal outputting the first prescribed potential. The potential generator circuit outputs the second power supply potential when the second power supply potential is higher than a predetermined potential, and the first power supply potential when the second power supply potential is lower than the predetermined potential.
摘要翻译：半导体器件包括第一晶体管和电位发生器电路。第一晶体管具有形成在第一半导体区域中的第一导电型第一半导体区域和第二导电型第二半导体区域。第一和第二半导体区域分别被提供第一和第二规定电位。电位发生器电路产生第一规定电位。电位发生器电路具有被提供有第一电源电位的第一电源端子，被提供有设置为比第一电源电位高的电位的第二电源电位的第二电源端子以及输出第一规定潜在。当第二电源电位高于预定电位时，电位发生器电路输出第二电源电位，而当第二电源电位低于预定电位时，该第一电源电位。

24. 发明授权

US08797807B2 Semiconductor memory and semiconductor memory control method 有权
标题翻译：半导体存储器和半导体存储器控制方法
公开(公告)号：US08797807B2
公开(公告)日：2014-08-05
申请号：US13432708
申请日：2012-03-28
申请人： Masahiro Yoshihara , Katsumi Abe
发明人： Masahiro Yoshihara , Katsumi Abe
IPC分类号： G11C7/10 , G11C16/10 , G11C16/26
CPC分类号： G11C7/1078 , G11C7/08 , G11C7/1051 , G11C7/106 , G11C7/1087 , G11C7/12 , G11C7/22 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C2207/2227 , G11C2207/2245
摘要： According to one embodiment, the semiconductor memory includes a memory cell array which includes memory cells to store data, a buffer circuit which includes latches, each of the latches including transistors as control elements and a flip-flop, and a control circuit which turns off the transistors to deactivate one or more of the latches.
摘要翻译：根据一个实施例，半导体存储器包括存储单元阵列，其包括用于存储数据的存储单元，包括锁存器的缓冲电路，每个锁存器包括作为控制元件的晶体管和触发器，以及控制电路，晶体管去激活一个或多个锁存器。

25. 发明授权

US08599613B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08599613B2
公开(公告)日：2013-12-03
申请号：US13428914
申请日：2012-03-23
申请人： Naofumi Abiko , Masahiro Yoshihara
发明人： Naofumi Abiko , Masahiro Yoshihara
IPC分类号： G11C16/00
CPC分类号： G11C16/26 , G11C16/32 , G11C16/3459 , G11C29/702
摘要： According to one embodiment, a nonvolatile semiconductor memory includes a memory cell array including memory cells of a first unit in which read and write are parallelly performed, n (n is a natural number of not less than 2) sense amplifiers, n detection circuits corresponding to the n sense amplifiers, an accumulator configured to divide the first unit data read from the memory cell array into z (z is a natural number) second unit data and accumulate a fail bit for which the write is incomplete for the second unit data, and a control circuit configured to control an operation of detecting the fail bit after the write.
摘要翻译：根据一个实施例，非易失性半导体存储器包括存储单元阵列，其包括并行执行读和写的第一单元的存储单元，n（n是不少于2个的自然数）读出放大器，n个检测电路对应配置成将从存储单元阵列读出的第一单位数据分割为z（z为自然数）第二单位数据的累加器，并累加第二单位数据写入不完整的故障位，以及控制电路，被配置为控制在写入之后检测故障位的操作。

26. 发明授权

US08559226B2 Threshold detecting method and verify method of memory cells 有权
标题翻译：存储单元的阈值检测方法和验证方法
公开(公告)号：US08559226B2
公开(公告)日：2013-10-15
申请号：US13052148
申请日：2011-03-21
申请人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
发明人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/12 , G11C16/32 , G11C16/3468
摘要： According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the memory cells and a node corresponding to the bit line, while a potential of the word line is kept constant.
摘要翻译：根据一个实施例，用于检测非易失性半导体存储单元的阈值的阈值检测方法包括：将预设电压施加到连接到存储单元的字线，以及在放电期间的两个不同定时执行位线检测线连接到存储器单元和对应于位线的节点，而字线的电位保持恒定。

27. 发明授权

US08472248B2 Semiconductor memory and control method thereof 有权
标题翻译：半导体存储器及其控制方法
公开(公告)号：US08472248B2
公开(公告)日：2013-06-25
申请号：US13235430
申请日：2011-09-18
申请人： Hiroyuki Kaga , Masahiro Yoshihara , Naofumi Abiko
发明人： Hiroyuki Kaga , Masahiro Yoshihara , Naofumi Abiko
IPC分类号： G11C11/34
CPC分类号： G11C11/4096 , G11C11/5642 , G11C16/0483 , G11C16/08
摘要： According to one embodiment, a semiconductor memory includes a memory cell array which includes memory cells, the memory cells being arranged along a row direction and a column direction and storing data respectively corresponding to thresholds, a row control circuit which controls a row of the memory cell array, and a column control circuit which includes a control unit, the control unit generating a signal to control elements corresponding to column of the memory cell array in accordance with a pointer corresponding to an external address signal.
摘要翻译：根据一个实施例，半导体存储器包括存储单元阵列，存储单元阵列包括存储单元，存储单元沿着行方向和列方向排列，并且分别存储对应于阈值的数据，控制存储器行的行控制电路单元阵列和列控制电路，其包括控制单元，所述控制单元根据与外部地址信号对应的指针，产生对应于存储单元阵列的列的控制元件的信号。

28. 发明申请

US20120250425A1 SEMICONDUCTOR MEMORY AND SEMICONDUCTOR MEMORY CONTROL METHOD 有权
标题翻译：半导体存储器和半导体存储器控制方法
公开(公告)号：US20120250425A1
公开(公告)日：2012-10-04
申请号：US13432708
申请日：2012-03-28
申请人： Masahiro YOSHIHARA , Katsumi ABE
发明人： Masahiro YOSHIHARA , Katsumi ABE
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/08 , G11C7/1051 , G11C7/106 , G11C7/1087 , G11C7/12 , G11C7/22 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C2207/2227 , G11C2207/2245
摘要： According to one embodiment, the semiconductor memory includes a memory cell array which includes memory cells to store data, a buffer circuit which includes latches, each of the latches including transistors as control elements and a flip-flop, and a control circuit which turns off the transistors to deactivate one or more of the latches.
摘要翻译：根据一个实施例，半导体存储器包括存储单元阵列，其包括用于存储数据的存储单元，包括锁存器的缓冲电路，每个锁存器包括作为控制元件的晶体管和触发器，以及控制电路，晶体管去激活一个或多个锁存器。

29. 发明申请

US20120250411A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20120250411A1
公开(公告)日：2012-10-04
申请号：US13428914
申请日：2012-03-23
申请人： Naofumi ABIKO , Masahiro Yoshihara
发明人： Naofumi ABIKO , Masahiro Yoshihara
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C16/32 , G11C16/3459 , G11C29/702
摘要： According to one embodiment, a nonvolatile semiconductor memory includes a memory cell array including memory cells of a first unit in which read and write are parallelly performed, n (n is a natural number of not less than 2) sense amplifiers, n detection circuits corresponding to the n sense amplifiers, an accumulator configured to divide the first unit data read from the memory cell array into z (z is a natural number) second unit data and accumulate a fail bit for which the write is incomplete for the second unit data, and a control circuit configured to control an operation of detecting the fail bit after the write.
摘要翻译：根据一个实施例，非易失性半导体存储器包括存储单元阵列，其包括并行执行读和写的第一单元的存储单元，n（n是不少于2个的自然数）读出放大器，n个检测电路对应配置成将从存储单元阵列读出的第一单位数据分割为z（z为自然数）第二单位数据的累加器，并累加第二单位数据写入不完整的故障位，以及控制电路，被配置为控制在写入之后检测故障位的操作。

30. 发明申请

US20110305089A1 THRESHOLD DETECTING METHOD AND VERIFY METHOD OF MEMORY CELLS 有权
标题翻译：记忆细胞的阈值检测方法和验证方法
公开(公告)号：US20110305089A1
公开(公告)日：2011-12-15
申请号：US13052148
申请日：2011-03-21
申请人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
发明人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
IPC分类号： G11C16/34 , G11C16/26 , G11C16/12 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/12 , G11C16/32 , G11C16/3468
摘要： According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the memory cells and a node corresponding to the bit line, while a potential of the word line is kept constant.
摘要翻译：根据一个实施例，用于检测非易失性半导体存储单元的阈值的阈值检测方法包括：将预设电压施加到连接到存储单元的字线，以及在放电期间的两个不同定时执行位线检测线连接到存储器单元和对应于位线的节点，而字线的电位保持恒定。

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