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21. 发明申请

US20090067259A1 SEMICONDUCTOR MEMORY DEVICE CONFIGURED TO REDUCE CURRENT CONSUMPTION ASSOCIATED WITH CRITICAL EVALUATING OF DATA WRITE OPERATIONS 审中-公开
标题翻译：半导体存储器件被配置为减少与数据写入操作的关键评估相关的消耗电流
公开(公告)号：US20090067259A1
公开(公告)日：2009-03-12
申请号：US12198225
申请日：2008-08-26
申请人： Ki Chon PARK
发明人： Ki Chon PARK
IPC分类号： G11C7/00
CPC分类号： G11C7/10 , G11C7/1006 , G11C7/1012 , G11C7/1078 , G11C7/1096
摘要： A semiconductor memory device that utilizes a routing controller and various specific operational modes for reducing current consumption during data write pass operations. The semiconductor memory device includes write pass corresponding to first pad which transfer any one of general data and representative data corresponding to specific mode; and a routing controller routing the representative data to transfer pass corresponding to second pad according to the specific operational mode and upon deviating from the mode, interrupting the routing of the general data to the transfer pass.
摘要翻译：一种半导体存储器件，其利用路由控制器和各种特定操作模式以减少数据写入通过操作期间的电流消耗。半导体存储器件包括对应于第一焊盘的写入通道，该第一焊盘传送与特定模式对应的一般数据和代表性数据中的任何一个; 以及路由控制器，根据特定操作模式将代表性数据路由到与第二焊盘相对应的传输通道，并且在偏离模式时，中断通用数据到传输通路的路由。

22. 发明申请

US20090067258A1 SEMICONDUCTOR MEMORY DEVICE HAVING A CURRENT CONSUMPTION REDUCTION IN A DATA WRITE PATH 失效
标题翻译：在数据写入路径中减少消耗电流的半导体存储器件
公开(公告)号：US20090067258A1
公开(公告)日：2009-03-12
申请号：US11964136
申请日：2007-12-26
申请人： Ki Chon PARK
发明人： Ki Chon PARK
IPC分类号： G11C7/00
CPC分类号： G11C7/10 , G11C7/1006 , G11C7/1012 , G11C7/1078 , G11C7/1096
摘要： The present invention describes a semiconductor memory device that can reduce current consumption occurring in a data write path. The semiconductor memory device includes a write path over which any one of general data and representative data corresponding to a particular mode is transferred in correspondence with a prescribed pad. A routing controller allows the representative data to be routed over a transfer path corresponding to any other pads in the particular mode and prevents the general data from being routed over the transfer path in modes other than the particular mode. The semiconductor memory device can reduce current consumption caused by unnecessary toggling of the data through utilization of the routing controller.
摘要翻译：本发明描述了可以减少在数据写入路径中发生的电流消耗的半导体存储器件。半导体存储器件包括与通常数据和对应于特定模式的代表数据中的任何一个对应于规定的焊盘传送的写入路径。路由控制器允许代表性数据通过与特定模式中的任何其它焊盘相对应的传输路径进行路由，并防止通用数据在特定模式以外的模式下通过传输路径进行路由。半导体存储器件可以通过利用路由控制器来减少由不必要的数据切换引起的电流消耗。

23. 发明申请

US20140088397A1 Fabrication and Use of Epidermal Electrodes 审中-公开
标题翻译：表皮电极的制造和使用
公开(公告)号：US20140088397A1
公开(公告)日：2014-03-27
申请号：US14028817
申请日：2013-09-17
申请人： Ki Chon , Justin Bales , Albert J. Swiston , Bersain A. Reyes , Hugo F. Posada-Quintero
发明人： Ki Chon , Justin Bales , Albert J. Swiston , Bersain A. Reyes , Hugo F. Posada-Quintero
IPC分类号： A61B5/0424 , B29C39/10
CPC分类号： A61B5/0424 , A61B2562/0215 , A61B2562/164 , B29C39/10 , Y10T29/49117
摘要： An epidermal electrode operable independently of the ambient environment, such as the presence of water, sweat, or dry conditions, and achieve a suitable impedance with the epidermal surface for transmitting electrical signals indicative of bodily physiological process such as ECG signals for heart monitoring. The hydrophobic surface mountable electrode including a flexible, conductive substrate of PDMS (Polydimethylsiloxane) with dispersed carbon black and having a substantially planar sensing area adapted for communication with an electrically sensitive surface such as a patient's skin, and a terminal for connection to a monitor circuit, the terminal having electrical continuity with the planar sensing area.
摘要翻译：可以独立于周围环境操作的表皮电极，例如存在水，汗水或干燥条件，并且与表皮表面实现适当的阻抗，用于传输指示身体生理过程的电信号，例如用于心脏监测的ECG信号。疏水性表面安装电极包括具有分散的炭黑并具有适于与诸如患者皮肤的电敏感表面通信的基本上平面的感测区域的PDMS的柔性导电基底（聚二甲基硅氧烷）和用于连接到监视器电路的端子，所述端子与所述平面感测区域具有电连续性。

24. 发明申请

US20120008451A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120008451A1
公开(公告)日：2012-01-12
申请号：US12914319
申请日：2010-10-28
申请人： Jae-Hoon Cha , Ki-Chon Park
发明人： Jae-Hoon Cha , Ki-Chon Park
IPC分类号： G11C8/12
CPC分类号： G11C8/12 , G11C7/1066 , G11C7/1072 , G11C8/18 , G11C11/4076 , G11C11/4087
摘要： A semiconductor memory device includes a first group configured to include a first bank and a second bank; a second group configured to include a third bank and a fourth bank; an address strobe pulse generating unit configured to generate an address strobe pulse signal for activating the first group and the second group in response to a first bank address and a command signal; and a strobe signal generating unit configured to generate a strobe signal that selects a bank from the first group and the second group in response to the address strobe pulse signal and a second bank address.
摘要翻译：半导体存储器件包括：第一组，其被配置为包括第一组和第二组; 第二组，被配置为包括第三组和第四组; 地址选通脉冲发生单元，被配置为响应于第一存储体地址和命令信号产生用于激活第一组和第二组的地址选通脉冲信号; 以及选通信号生成单元，被配置为响应于地址选通脉冲信号和第二存储体地址，生成从第一组和第二组中选择存储区的选通信号。

25. 发明授权

US07948807B2 Semiconductor memory device having a current consumption reduction in a data write path 失效
标题翻译：具有在数据写入路径中消耗电流消耗的半导体存储器件
公开(公告)号：US07948807B2
公开(公告)日：2011-05-24
申请号：US11964136
申请日：2007-12-26
申请人： Ki Chon Park
发明人： Ki Chon Park
IPC分类号： G11C7/10
CPC分类号： G11C7/10 , G11C7/1006 , G11C7/1012 , G11C7/1078 , G11C7/1096
摘要： The present invention describes a semiconductor memory device that can reduce current consumption occurring in a data write path. The semiconductor memory device includes a write path over which any one of general data and representative data corresponding to a particular mode is transferred in correspondence with a prescribed pad. A routing controller allows the representative data to be routed over a transfer path corresponding to any other pads in the particular mode and prevents the general data from being routed over the transfer path in modes other than the particular mode. The semiconductor memory device can reduce current consumption caused by unnecessary toggling of the data through utilization of the routing controller.
摘要翻译：本发明描述了可以减少在数据写入路径中发生的电流消耗的半导体存储器件。半导体存储器件包括与通常数据和对应于特定模式的代表数据中的任何一个对应于规定的焊盘传送的写入路径。路由控制器允许代表性数据通过与特定模式中的任何其它焊盘相对应的传输路径进行路由，并防止通用数据在特定模式以外的模式下通过传输路径进行路由。半导体存储器件可以通过利用路由控制器来减少由不必要的数据切换引起的电流消耗。

26. 发明授权

US07830728B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07830728B2
公开(公告)日：2010-11-09
申请号：US12327203
申请日：2008-12-03
申请人： Ki-Chon Park , Byoung-Jin Choi
发明人： Ki-Chon Park , Byoung-Jin Choi
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C7/1006 , G11C2207/107
摘要： Disclosed is a semiconductor memory device includes a selector for selectively loading read inversion information and write inversion information on an inversion bus, the inversion bus for transferring the inversion information loaded by the selector, a plurality of read inversion units for reflecting the inversion information from the inversion bus to output data, and a plurality of write inversion units for reflecting the inversion information from the inversion bus to input data.
摘要翻译：公开了一种半导体存储器件，包括：选择器，用于选择性地加载读取反相信息并在反相总线上写入反相信息，反转总线用于传送由选择器加载的反转信息;多个读取反转单元，用于反映来自反相总线输出数据，以及多个写反转单元，用于将反转信息从反转总线反映到输入数据。

27. 发明申请

US20100077125A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100077125A1
公开(公告)日：2010-03-25
申请号：US12327203
申请日：2008-12-03
申请人： Ki-Chon PARK , Byoung-Jin CHOI
发明人： Ki-Chon PARK , Byoung-Jin CHOI
IPC分类号： G06F13/372
CPC分类号： G11C7/02 , G11C7/1006 , G11C2207/107
摘要： Disclosed is a semiconductor memory device includes a selector for selectively loading read inversion information and write inversion information on an inversion bus, the inversion bus for transferring the inversion information loaded by the selector, a plurality of read inversion units for reflecting the inversion information from the inversion bus to output data, and a plurality of write inversion units for reflecting the inversion information from the inversion bus to input data.
摘要翻译：公开了一种半导体存储器件，包括：选择器，用于选择性地加载读取反相信息并在反相总线上写入反相信息，反转总线用于传送由选择器加载的反转信息;多个读取反转单元，用于反映来自反相总线输出数据，以及多个写反转单元，用于将反转信息从反转总线反映到输入数据。

28. 发明申请

US20100052779A1 DOHERTY AMPLIFIER AND SIGNAL AMPLIFICATION SYSTEM HAVING THE SAME, METHOD FOR AMPLIFYING SIGNAL 失效
标题翻译：具有该功能的DOHERTY放大器和信号放大系统，放大信号的方法
公开(公告)号：US20100052779A1
公开(公告)日：2010-03-04
申请号：US12545961
申请日：2009-08-24
申请人： Jin Ho SHIN , Ki Chon HAN
发明人： Jin Ho SHIN , Ki Chon HAN
IPC分类号： H03F3/68
CPC分类号： H03F1/302 , H03F1/0288 , H03F1/56 , H03F2200/18 , H03F2200/447
摘要： A Doherty amplifier is provided. The Doherty amplifier includes a first path circuit including a carrier amplifier and a first impedance adjusting circuit connected with the carrier amplifier; and a second path circuit including a peaking amplifier, a second impedance adjusting circuit connected with the peaking amplifier, and a peaking amplifier bias circuit connected with the peaking amplifier. At least one among an impedance of the first impedance adjusting circuit, an impedance of the second impedance adjusting circuit, and a bias of the peaking amplifier bias circuit is adjusted in response to a control signal.
摘要翻译：提供了Doherty放大器。多赫蒂放大器包括第一路径电路，其包括载波放大器和与载波放大器连接的第一阻抗调节电路; 以及第二路径电路，包括峰值放大器，与峰化放大器连接的第二阻抗调整电路，以及与峰值放大器连接的峰值放大器偏置电路。响应于控制信号调整第一阻抗调整电路的阻抗，第二阻抗调整电路的阻抗和峰化放大器偏置电路的偏置中的至少一个。

29. 发明申请

US20090168568A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20090168568A1
公开(公告)日：2009-07-02
申请号：US12165097
申请日：2008-06-30
申请人： Ki-Chon PARK
发明人： Ki-Chon PARK
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/222
摘要： A semiconductor memory device can output data according to a predetermined data output timing, in spite of a high frequency of system clock, even when a delay locked loop is disabled. The semiconductor memory device includes a delay locked loop configured to perform a delay locking operation on an internal clock to output delay locked clock, and a data output control unit configured to determine a data output timing, according to whether the delay locked loop is enabled or disabled, in response to a read command.
摘要翻译：即使当延迟锁定环被禁用时，半导体存储器件也可以根据预定的数据输出定时输出数据，尽管存在系统时钟的高频率。半导体存储器件包括延迟锁定回路，被配置为对内部时钟执行延迟锁定操作以输出延迟锁定时钟;以及数据输出控制单元，被配置为根据延迟锁定环路是启用还是确定数据输出定时，禁用，响应于读命令。

30. 发明申请

US20080239862A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20080239862A1
公开(公告)日：2008-10-02
申请号：US12003679
申请日：2007-12-31
申请人： Jae-Hoon Cha , Ki-Chon Park
发明人： Jae-Hoon Cha , Ki-Chon Park
IPC分类号： G11C8/12
CPC分类号： G11C8/12
摘要： The present invention provides a semiconductor memory device that can reduce unnecessary current consumption, as banks not accessing data maintain an inactivation state and do not receive an input address. A semiconductor memory device includes a plurality of banks grouped into a first group and a second group; and a bank control unit for selecting one of the first group and the second group in response to a bank address to transfer an address to the selected group.
摘要翻译：本发明提供一种可以减少不必要的电流消耗的半导体存储器件，因为不存取数据的存储体保持失活状态并且不接收输入地址。半导体存储器件包括分组成第一组和第二组的多个存储体; 以及存储体控制单元，用于响应于存储体地址选择第一组和第二组中的一个，以将地址传送到所选择的组。

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