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21. 发明申请

US20120069670A1 Semiconductor Integrated Circuit Device for Driving Liquid Crystal Display 有权
标题翻译：用于驱动液晶显示器的半导体集成电路装置
公开(公告)号：US20120069670A1
公开(公告)日：2012-03-22
申请号：US13305532
申请日：2011-11-28
申请人： Yasushi Kawase , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
发明人： Yasushi Kawase , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
IPC分类号： G11C11/34
CPC分类号： G09G3/3655 , G09G5/005 , G09G2310/08 , H01L27/0207 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.
摘要翻译：本发明实现了一种用于驱动液晶（液晶控制驱动器IC）的半导体集成电路器件，其能够根据要使用的液晶显示器的规格容易地设置驱动条件等。在用于驱动液晶显示器的半导体集成电路器件中提供电可编程非易失性存储器电路（EPROM）或电可擦除和可编程的非易失性存储器电路（EEPROM），并将设置信息存储在存储器电路中。存储电路由与其他电路的形成器件的半导体制造工艺相同的工艺形成的普通器件构成。

22. 发明授权

US08084303B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08084303B2
公开(公告)日：2011-12-27
申请号：US12771673
申请日：2010-04-30
申请人： Kazuyoshi Shiba , Hideyuki Yashima
发明人： Kazuyoshi Shiba , Hideyuki Yashima
IPC分类号： H01L21/82
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11526 , H01L29/66825 , H01L29/7833 , H01L29/7883
摘要： In a memory cell array on a main surface of a semiconductor substrate, a floating gate electrode for accumulating charges for information is arranged. The floating gate electrode is covered with a cap insulating film and a pattern of an first insulating film formed thereon. Further, over the entire main surface of the semiconductor substrate, an second insulating film is deposited so that it covers the pattern of the first insulating film and a gate electrode. The second insulating film is formed by a silicon nitride film formed by a plasma CVD method. The first insulating film is formed by a silicon nitride film formed by a low-pressure CVD method. By the provision of such an first insulating film, it is possible to suppress or prevent water or hydrogen ions from diffusing to the floating gate electrode, and therefore, the data retention characteristics of a flash memory can be improved.
摘要翻译：在半导体衬底的主表面上的存储单元阵列中，布置用于累积信息电荷的浮栅电极。浮栅电极覆盖有帽绝缘膜和形成在其上的第一绝缘膜的图案。此外，在半导体基板的整个主表面上沉积第二绝缘膜，以覆盖第一绝缘膜和栅电极的图案。第二绝缘膜由通过等离子体CVD法形成的氮化硅膜形成。第一绝缘膜由通过低压CVD方法形成的氮化硅膜形成。通过设置这样的第一绝缘膜，可以抑制或防止水或氢离子扩散到浮栅电极，因此可以提高闪速存储器的数据保持特性。

23. 发明申请

US20100219458A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100219458A1
公开(公告)日：2010-09-02
申请号：US12771673
申请日：2010-04-30
申请人： KAZUYOSHI SHIBA , Hideyuki Yashima
发明人： KAZUYOSHI SHIBA , Hideyuki Yashima
IPC分类号： H01L27/105 , H01L29/788
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11526 , H01L29/66825 , H01L29/7833 , H01L29/7883
摘要： The data retention characteristics of a nonvolatile memory circuit are improved. In a memory cell array on a main surface of a semiconductor substrate, a floating gate electrode for accumulating charges for information is arranged. The floating gate electrode is covered with a cap insulating film and a pattern of an insulating film 4a formed thereon. Further, over the entire main surface of the semiconductor substrate, an insulating film 2a is deposited so that it covers the pattern of the insulating film 4a and a gate electrode. The insulating film 2a is formed by a silicon nitride film formed by the plasma CVD method. The insulating film 4a is formed by a silicon nitride film formed by the low-pressure CVD method. By the provision of such an insulating film 4a, it is possible to suppress or prevent water or hydrogen ions from diffusing to the floating gate electrode, and therefore, the data retention characteristics of a flash memory can be improved.
摘要翻译：提高了非易失性存储器电路的数据保持特性。在半导体衬底的主表面上的存储单元阵列中，布置用于累积信息电荷的浮栅电极。浮栅电极覆盖有帽绝缘膜和形成在其上的绝缘膜4a的图案。此外，在半导体基板的整个主表面上沉积绝缘膜2a，以覆盖绝缘膜4a和栅电极的图案。绝缘膜2a由通过等离子体CVD法形成的氮化硅膜形成。绝缘膜4a由通过低压CVD法形成的氮化硅膜形成。通过设置这样的绝缘膜4a，可以抑制或防止水或氢离子扩散到浮栅电极，因此可以提高闪存的数据保持特性。

24. 发明授权

US07639541B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07639541B2
公开(公告)日：2009-12-29
申请号：US11971546
申请日：2008-01-09
申请人： Kazuyoshi Shiba , Yasushi Oka
发明人： Kazuyoshi Shiba , Yasushi Oka
IPC分类号： G11C11/03
CPC分类号： H01L27/115 , G11C16/0441 , G11C2216/26 , H01L27/11521 , H01L27/11558
摘要： A semiconductor device includes a circuit forming area and a memory area including memory cells, first and second wells, a first conductor film formed over both wells and a second conductor film formed over the first well. First semiconductor regions are formed in the first region and a second semiconductor region is formed in the second region. The memory cells each include a capacitance element, including the first conductor film and second region, an element for reading data, including the first conductor film and first regions, and a selection field effect transistor, including the second conductor film and first regions. A length of the first conductor film of the capacitance element is larger than a length of the first conductor film of the element for reading data. A word line of the memory cell is connected to the second semiconductor region. During a reading data operation, a first bit line of the memory cell is connected to the first semiconductor region of the element for reading data via the selection field effect transistor.
摘要翻译：半导体器件包括电路形成区域和包括存储单元，第一和第二阱，形成在两个阱上的第一导体膜和形成在第一阱上的第二导体膜的存储区域。第一半导体区域形成在第一区域中，并且在第二区域中形成第二半导体区域。存储单元各自包括包括第一导体膜和第二区域的电容元件，包括第一导体膜和第一区域的用于读取数据的元件，以及包括第二导体膜和第一区域的选择场效应晶体管。电容元件的第一导体膜的长度大于用于读取数据的元件的第一导体膜的长度。存储单元的字线连接到第二半导体区域。在读取数据操作期间，存储单元的第一位线连接到用于经由选择场效应晶体管读取数据的元件的第一半导体区域。

25. 发明授权

US07601581B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07601581B2
公开(公告)日：2009-10-13
申请号：US11649759
申请日：2007-01-05
申请人： Yasuhiro Taniguchi , Kazuyoshi Shiba
发明人： Yasuhiro Taniguchi , Kazuyoshi Shiba
IPC分类号： H01L21/8238
CPC分类号： H01L21/823462 , H01L27/0629 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573
摘要： Provided is a manufacturing method of a semiconductor device, which comprises forming a film stack of a gate insulating film, a charge storage film, insulating film, polysilicon film, silicon oxide film, silicon nitride film and cap insulating film over a semiconductor substrate; removing the film stack by photolithography and etching from a low breakdown voltage MISFET formation region and a high breakdown voltage MISFET formation region; forming gate insulating films, polysilicon film and cap insulating film over the semiconductor substrate, forming a gate electrode in the low breakdown voltage MISFET formation region and high breakdown voltage MISFET formation region, and then forming a gate electrode in a memory cell formation region. By the manufacturing technology of a semiconductor device for forming the gate electrodes of a first MISFET and a second MISFET in different steps, the present invention makes it possible to provide the first MISFET and the second MISFET each having improved reliability.
摘要翻译：提供一种半导体器件的制造方法，其包括在半导体衬底上形成栅极绝缘膜，电荷存储膜，绝缘膜，多晶硅膜，氧化硅膜，氮化硅膜和帽绝缘膜的膜堆叠; 通过光刻和蚀刻从低击穿电压MISFET形成区域和高击穿电压MISFET形成区域去除膜堆叠; 在半导体衬底上形成栅极绝缘膜，多晶硅膜和帽绝缘膜，在低击穿电压MISFET形成区域和高击穿电压MISFET形成区域中形成栅电极，然后在存储器单元形成区域中形成栅电极。通过以不同的步骤形成第一MISFET和第二MISFET的栅极的半导体器件的制造技术，本发明使得可以提供具有改善的可靠性的第一MISFET和第二MISFET。

26. 发明申请

US20090008690A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090008690A1
公开(公告)日：2009-01-08
申请号：US12137955
申请日：2008-06-12
申请人： Kazuyoshi SHIBA , Hideyuki Yashima
发明人： Kazuyoshi SHIBA , Hideyuki Yashima
IPC分类号： H01L27/108 , H01L29/788 , H01L21/336
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11526 , H01L29/66825 , H01L29/7833 , H01L29/7883
摘要： The data retention characteristics of a nonvolatile memory circuit are improved. In a memory cell array on a main surface of a semiconductor substrate, a floating gate electrode for accumulating charges for information is arranged. The floating gate electrode is covered with a cap insulating film and a pattern of an insulating film 4a formed thereon. Further, over the entire main surface of the semiconductor substrate, an insulating film 2a is deposited so that it covers the pattern of the insulating film 4a and a gate electrode. The insulating film 2a is formed by a silicon nitride film formed by the plasma CVD method. The insulating film 4a is formed by a silicon nitride film formed by the low-pressure CVD method. By the provision of such an insulating film 4a, it is possible to suppress or prevent water or hydrogen ions from diffusing to the floating gate electrode, and therefore, the data retention characteristics of a flash memory can be improved.
摘要翻译：提高了非易失性存储器电路的数据保持特性。在半导体衬底的主表面上的存储单元阵列中，布置用于累积信息电荷的浮栅电极。浮栅电极覆盖有帽绝缘膜和形成在其上的绝缘膜4a的图案。此外，在半导体基板的整个主表面上沉积绝缘膜2a，以覆盖绝缘膜4a和栅电极的图案。绝缘膜2a由通过等离子体CVD法形成的氮化硅膜形成。绝缘膜4a由通过低压CVD法形成的氮化硅膜形成。通过设置这样的绝缘膜4a，可以抑制或防止水或氢离子扩散到浮栅电极，因此可以提高闪存的数据保持特性。

27. 发明申请

US20080028134A1 DATA LINE DISTURBANCE FREE MEMORY BLOCK DIVIDED FLASH MEMORY AND MICROCOMPUTER HAVING FLASH MEMORY THEREIN 失效
标题翻译：数据线干扰免费内存块分割闪存和具有闪存存储器的微型计算机
公开(公告)号：US20080028134A1
公开(公告)日：2008-01-31
申请号：US11860762
申请日：2007-09-25
申请人： Kiyoshi MATSUBARA , Naoki Yashiki , Shiro Baba , Takashi Ito , Hirofumi Mukai , Masanao Sato , Masaaki Terasawa , Kenichi Kuroda , Kazuyoshi Shiba
发明人： Kiyoshi MATSUBARA , Naoki Yashiki , Shiro Baba , Takashi Ito , Hirofumi Mukai , Masanao Sato , Masaaki Terasawa , Kenichi Kuroda , Kazuyoshi Shiba
IPC分类号： G06F13/00
CPC分类号： H01L27/11526 , G06F9/445 , G06F15/7814 , G06F15/7821 , G11C7/1045 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11546 , Y02D10/43
摘要： A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.
摘要翻译：具有电可擦除和可编程非易失性存储器的半导体器件，例如，包括以行和列布置的存储器单元的可重写非易失性存储器，并且被设置为便于闪存擦除以及多个存储器单元的各个单元的选择性擦除。用作微计算机芯片的半导体器件还具有处理单元，并且包括：输入端子，用于在处理单元的控制下在闪速存储器被重写的第一操作模式和第二操作模式之间接收用于切换微型计算机的操作模式信号操作模式，其中在外部连接到微型计算机的分离的写入电路的控制下闪存被重写。

28. 发明申请

US20070207575A1 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20070207575A1
公开(公告)日：2007-09-06
申请号：US11649759
申请日：2007-01-05
申请人： Yasuhiro Taniguchi , Kazuyoshi Shiba
发明人： Yasuhiro Taniguchi , Kazuyoshi Shiba
IPC分类号： H01L21/8238
CPC分类号： H01L21/823462 , H01L27/0629 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573
摘要： Provided is a manufacturing method of a semiconductor device, which comprises forming a film stack of a gate insulating film, a charge storage film, insulating film, polysilicon film, silicon oxide film, silicon nitride film and cap insulating film over a semiconductor substrate; removing the film stack by photolithography and etching from a low breakdown voltage MISFET formation region and a high breakdown voltage MISFET formation region; forming gate insulating films, polysilicon film and cap insulating film over the semiconductor substrate, forming a gate electrode in the low breakdown voltage MISFET formation region and high breakdown voltage MISFET formation region, and then forming a gate electrode in a memory cell formation region. By the manufacturing technology of a semiconductor device for forming the gate electrodes of a first MISFET and a second MISFET in different steps, the present invention makes it possible to provide the first MISFET and the second MISFET each having improved reliability.
摘要翻译：提供一种半导体器件的制造方法，其包括在半导体衬底上形成栅极绝缘膜，电荷存储膜，绝缘膜，多晶硅膜，氧化硅膜，氮化硅膜和帽绝缘膜的膜堆叠; 通过光刻和蚀刻从低击穿电压MISFET形成区域和高击穿电压MISFET形成区域去除膜堆叠; 在半导体衬底上形成栅极绝缘膜，多晶硅膜和帽绝缘膜，在低击穿电压MISFET形成区域和高击穿电压MISFET形成区域中形成栅电极，然后在存储器单元形成区域中形成栅电极。通过以不同的步骤形成第一MISFET和第二MISFET的栅极的半导体器件的制造技术，本发明使得可以提供具有改善的可靠性的第一MISFET和第二MISFET。

29. 发明授权

US06842376B2 Non-volatile semiconductor memory device for selectively re-checking word lines 有权
标题翻译：用于选择性地重新检查字线的非易失性半导体存储器件
公开(公告)号：US06842376B2
公开(公告)日：2005-01-11
申请号：US10638491
申请日：2003-08-12
申请人： Nozomu Matsuzaki , Kazuyoshi Shiba , Yasuhiro Taniguchi , Toshihiro Tanaka , Yutaka Shinagawa
发明人： Nozomu Matsuzaki , Kazuyoshi Shiba , Yasuhiro Taniguchi , Toshihiro Tanaka , Yutaka Shinagawa
IPC分类号： G11C16/06 , G11C8/08 , G11C16/02 , G11C16/12 , G11C16/34 , G11C16/04
CPC分类号： G11C16/3409 , G11C8/08 , G11C16/12 , G11C16/3404
摘要： A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.
摘要翻译：一种用于在非易失性半导体存储器件的擦除处理中在预定电平上建立字线的阈值电压的方法，以加速擦除处理。为每个字线提供字锁存电路，并且在所选择的存储器块中为每个字线管理每个存储器单元的阈值电压。每个字锁存电路由多个字线共享，以便减少所需的芯片面积。为每个完成的非易失性存储器设置重写电压，并且电压信息被存储在非易失性存储器的引导区域中，使得每当系统供电时，系统识别电压。

30. 发明授权

US06480418B2 Semiconductor non-volatile storage 有权
标题翻译：半导体非易失性存储
公开(公告)号：US06480418B2
公开(公告)日：2002-11-12
申请号：US09951979
申请日：2001-09-14
申请人： Toshihiro Tanaka , Yutaka Shinagawa , Kazuyoshi Shiba , Kazufumi Suzukawa , Masamichi Fujito , Takayuki Oshima , Sonoko Abe , Kiyoshi Matsubara
发明人： Toshihiro Tanaka , Yutaka Shinagawa , Kazuyoshi Shiba , Kazufumi Suzukawa , Masamichi Fujito , Takayuki Oshima , Sonoko Abe , Kiyoshi Matsubara
IPC分类号： G11C1604
CPC分类号： G11C16/0416 , G11C16/24 , G11C16/30
摘要： The present invention proposes a non-volatile semiconductor storage, comprising a plurality of main bit lines, a plurality of sub bit lines connected to the main bit lines, and a plurality of memory cell arrays, each including a plurality of non-volatile semiconductor memory cells disposed like an array. Each of those memory cells has a source terminal, a drain terminal, and a control gate, and each source-drain path is connected to a sub bit line. Between a main bit line and a sub bit line connected to the main bit line is disposed the source-drain path of a first transistor, and the source-drain path of a second transistor is connected to the sub bit line.
摘要翻译：本发明提出了一种非易失性半导体存储器，包括多个主位线，连接到主位线的多个子位线以及多个存储单元阵列，每个存储单元阵列包括多个非易失性半导体存储器细胞排列成阵列。这些存储单元中的每一个具有源极端子，漏极端子和控制栅极，并且每个源极 - 漏极路径连接到子位线。在主位线和连接到主位线的子位线之间设置第一晶体管的源极 - 漏极路径，并且第二晶体管的源极 - 漏极路径连接到子位线。

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