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21. 发明申请

US20050056921A1 Stacked module systems and methods 审中-公开
标题翻译：堆叠模块系统和方法
公开(公告)号：US20050056921A1
公开(公告)日：2005-03-17
申请号：US10845029
申请日：2004-05-13
申请人： James Wehrly , James Cady , Julian Partridge , David Roper
发明人： James Wehrly , James Cady , Julian Partridge , David Roper
IPC分类号： H01L23/31 , H01L23/498 , H01L25/065 , H01L25/10 , H01L23/02
CPC分类号： H01L25/105 , H01L23/3114 , H01L23/4985 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73253 , H01L2225/107
摘要： The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or more conductive layers with preferred embodiments having two conductive layers. A form standard is disposed along the lower planar surface and extends laterally beyond the package of one or more CSPs in a stacked module. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be comprised of heat conductive material such as copper, for example.
摘要翻译：本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。根据本发明设计的堆叠模块中采用的CSP与柔性电路连接。该柔性电路可以呈现一个或多个导电层，优选实施例具有两个导电层。形式标准沿着下平面表面设置并横向延伸超过堆叠模块中的一个或多个CSP的包装。形式标准提供了一种物理形式，允许在采用标准连接柔性电路设计时，在广泛的CSP封装系列中发现许多变化的封装尺寸。在优选实施例中，形式标准例如由导热材料例如铜构成。

22. 发明申请

US20050009234A1 Stacked module systems and methods for CSP packages 审中-公开
标题翻译： CSP封装的堆叠模块系统和方法
公开(公告)号：US20050009234A1
公开(公告)日：2005-01-13
申请号：US10913220
申请日：2004-08-06
申请人： Julian Partridge , James Wehrly , Julian Dowden , David Roper , James Cady
发明人： Julian Partridge , James Wehrly , Julian Dowden , David Roper , James Cady
IPC分类号： H01L23/31 , H01L23/498 , H01L23/538 , H01L25/10 , H05K1/14 , H05K1/18 , H05K3/36 , H01L21/44 , H01L23/02
CPC分类号： H01L23/3114 , H01L23/13 , H01L23/49816 , H01L23/4985 , H01L23/5387 , H01L25/105 , H01L2224/16237 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/01327 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2924/00
摘要： The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. Multiple numbers of CSPs may be stacked in accordance with the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. A form standard is disposed along a planar surface of a CSP. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. The form standard achieves a reduced profile after the CSP has been attached to the form standard. In addition, in constructing modules in accordance with some preferred modes of the invention, CSP contacts are reduced in height to create lower profile modules. Thus, low profile embodiments of the modules of the present invention are devised.
摘要翻译：本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。根据本发明可以堆叠多个CSP。根据本发明设计的堆叠模块中采用的CSP与柔性电路连接。形式标准沿着CSP的平面设置。形式标准提供了一种物理形式，允许在采用标准连接柔性电路设计时，在广泛的CSP封装系列中发现许多变化的封装尺寸。形式标准在CSP附加到表单标准之后实现了简化的简档。此外，在根据本发明的一些优选模式构建模块时，CSP触点的高度减小以形成下部轮廓模块。因此，设计了本发明的模块的低调实施例。

23. 发明授权

US07760513B2 Modified core for circuit module system and method 有权
标题翻译：电路模块系统和方法的改进核心
公开(公告)号：US07760513B2
公开(公告)日：2010-07-20
申请号：US11397597
申请日：2006-04-03
申请人： Julian Partridge , David Roper , Paul Goodwin
发明人： Julian Partridge , David Roper , Paul Goodwin
IPC分类号： H05K1/11
CPC分类号： H05K1/189 , H05K1/0203 , H05K1/11 , H05K1/181 , H05K3/0061 , H05K2201/056 , H05K2201/09445 , H05K2201/10159 , H05K2201/1056 , H05K2201/10734 , H05K2203/1572
摘要： Flexible circuitry is populated with integrated circuitry (ICs) disposed along one or both of its major sides. The populated flexible circuitry is disposed proximal to a rigid substrate to place the integrated circuitry on one or both sides of the substrate with one or two layers of integrated circuitry on one or both sides of the substrate. The rigid substrate exhibits adhesion features that allow more advantageous use of thermoplastic adhesives with concomitant rework advantages and while providing flexibility in meeting dimensional specifications such as those promulgated by JEDEC, for example.
摘要翻译：灵活的电路填充有沿其主要一侧或两侧设置的集成电路（IC）。填充的柔性电路设置在刚性衬底附近，以将集成电路放置在衬底的一侧或两侧上，在衬底的一侧或两侧上具有一层或两层集成电路。刚性基材表现出粘合特征，其允许更有利地使用具有伴随返工优点的热塑性粘合剂，并且同时提供满足例如由JEDEC公布的尺寸规格的柔性。

24. 发明申请

US20090309214A1 Circuit Module Turbulence Enhancement 审中-公开
标题翻译：电路模块湍流增强
公开(公告)号：US20090309214A1
公开(公告)日：2009-12-17
申请号：US12546350
申请日：2009-08-24
申请人： Leland Szewerenko , Julian Partridge , Wayne Lieberman , Paul Goodwin
发明人： Leland Szewerenko , Julian Partridge , Wayne Lieberman , Paul Goodwin
IPC分类号： H01L23/34 , H01L21/00 , H05K7/20
CPC分类号： H01L23/467 , H01L2924/0002 , H01L2924/00
摘要： Turbulence inducers are provided on circuit modules. Rising above a substrate or heat spreader surface, turbulence generators may be added to existing modules or integrated into substrates or heat spreaders employed by circuit modules constructed according to traditional or new technologies.
摘要翻译：在电路模块上提供湍流诱发器。在基板或散热器表面上方，可将湍流发生器添加到现有模块中，或者集成到基于传统或新技术构建的电路模块所采用的基板或散热器中。

25. 发明授权

US07626273B2 Low profile stacking system and method 有权
标题翻译：薄型堆叠系统和方法
公开(公告)号：US07626273B2
公开(公告)日：2009-12-01
申请号：US12356432
申请日：2009-01-20
申请人： Julian Partridge , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr.
发明人： Julian Partridge , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr.
IPC分类号： H01L23/538
CPC分类号： H01L25/0657 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/105 , H01L2224/13 , H01L2224/13099 , H01L2224/13111 , H01L2224/13116 , H01L2224/16237 , H01L2224/73253 , H01L2224/81011 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/8121 , H01L2224/81815 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/3463 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2924/00
摘要： The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.
摘要翻译：本发明提供了一种将集成电路器件安装到衬底上的系统和方法，以及用于将堆叠模块中采用该方法的系统和方法。封装的集成电路器件的接触焊盘基本上露出。将包括较高温度的焊膏合金的焊膏施加到要安装的基板或集成电路器件上。集成电路器件定位成与衬底的触点接触。施加热量以在基板的触点和集成电路装置之间形成高温接头，从而形成具有高温接头的装置 - 基板组件。形成的接头在随后的加工步骤中较少受到再熔化。该方法可以用于设计堆叠的模块结构，例如根据本发明的优选实施例中公开的那些。通常，创建的关节的轮廓较低。

26. 发明授权

US07573129B2 Contrast interposer stacking system and method 有权
标题翻译：对比度内插器堆叠系统和方法
公开(公告)号：US07573129B2
公开(公告)日：2009-08-11
申请号：US11533743
申请日：2006-09-20
申请人： Julian Partridge , Roel Perez , Leland Szewerenko
发明人： Julian Partridge , Roel Perez , Leland Szewerenko
IPC分类号： H01L23/02
CPC分类号： H01L25/105 , H01L2225/1029 , H01L2225/107 , H01L2924/0002 , H05K1/141 , H05K2201/049 , H05K2201/10378 , H05K2201/10515 , H05K2201/10689 , H01L2924/00
摘要： The present description provides increased contrast between interposer and leads in a stack embodiment that employs an interposer that extends beyond a boundary or perimeter established by the leads of the constituent IC devices.
摘要翻译：本描述提供了在堆叠实施例中的插入器和引线之间的增加的对比度，其采用延伸超过由组成IC器件的引线建立的边界或周边的插入器。

27. 发明授权

US07508069B2 Managed memory component 有权
标题翻译：托管内存组件
公开(公告)号：US07508069B2
公开(公告)日：2009-03-24
申请号：US11436946
申请日：2006-05-18
申请人： James Douglas Wehrly, Jr. , Ron Orris , Leland Szewerenko , Tim Roy , Julian Partridge , David L. Roper
发明人： James Douglas Wehrly, Jr. , Ron Orris , Leland Szewerenko , Tim Roy , Julian Partridge , David L. Roper
IPC分类号： H01L23/34
CPC分类号： H01L25/18 , H01L23/5387 , H01L25/105 , H01L2224/49175 , H01L2924/15311 , H05K1/147 , H05K1/189 , H05K3/326 , H05K3/3421 , H05K3/3436 , H05K3/3447 , H05K2201/055 , H05K2201/091 , H05K2201/09463 , H05K2201/10515 , H05K2201/10689
摘要： The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.
摘要翻译：本发明提供一种用于使用柔性电路组合引线封装IC和半导体管芯以减少组合的覆盖区的系统和方法。引线IC封装沿柔性电路的正面设置。在优选实施例中，引线IC封装的引线被配置为允许引线IC封装的主体的下表面通过粘合剂直接或间接地接触柔性电路的表面。半导体管芯连接到柔性电路的反面。在一个实施例中，半导体管芯设置在柔性反面的另一侧，而在替代实施例中，将半导体管芯设置在柔性电路中的窗口中，以直接或间接地安置在引线IC封装体上。模块触点以各种配置提供。在优选实施例中，引线IC封装是闪存，半导体管芯是控制器。

28. 发明申请

US20080211077A1 Low profile chip scale stacking system and method 审中-公开
标题翻译：薄型芯片级堆叠系统及方法
公开(公告)号：US20080211077A1
公开(公告)日：2008-09-04
申请号：US11432206
申请日：2006-05-11
申请人： James W. Cady , Julian Partridge , James Douglas Wehrly , James Wilder , David L. Roper , Jeffrey Alan Buchle
发明人： James W. Cady , Julian Partridge , James Douglas Wehrly , James Wilder , David L. Roper , Jeffrey Alan Buchle
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H05K1/141 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/73253 , H01L2224/81801 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/01322 , H01L2924/19041 , H01L2924/3011 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , Y10T29/49126 , Y10T29/49144
摘要： The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of methods and materials including, for example, screen paste techniques and use of high temperature solders, although other application techniques and traditional solders may be employed for creating low profile contacts in the present invention. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers. In some preferred embodiments, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In other embodiments, a heat spreader is disposed between the CSP and the flex circuitry thus providing an improved heat transference function without the standardization of the form standard, while still other embodiments lack either a form standard or a heat spreader and may employ, for example, the flex circuitry as a heat transference material.
摘要翻译：本发明将芯片级封装集成电路（CSP）堆叠成保留PWB或其他板表面积的低轮廓模块。薄型结构提供堆叠模块的CSP之间和柔性电路之间的连接。薄型触点由各种方法和材料中的任何一种产生，包括例如丝网糊技术和高温焊料的使用，尽管其它应用技术和传统焊料可用于在本发明中制造低轮廓触点。提供了一种合并的低轮廓接触结构和技术，用于本发明的替代实施例。根据本发明设计的堆叠模块中采用的CSP与柔性电路连接。该柔性电路可以表现出一个或两个或更多个导电层。在一些优选实施例中，形式标准提供了一种物理形式，其允许在采用标准连接柔性电路设计的同时，在广泛的CSP封装系列中发现许多变化的封装尺寸。在其他实施例中，散热器设置在CSP和柔性电路之间，从而提供改进的热传递功能，而不需要形式标准的标准化，而其它实施例还没有形式标准或散热器，并且可以采用例如，柔性电路作为热转移材料。

29. 发明授权

US07417310B2 Circuit module having force resistant construction 有权
标题翻译：电路模块具有抗压结构
公开(公告)号：US07417310B2
公开(公告)日：2008-08-26
申请号：US11556124
申请日：2006-11-02
申请人： Leland Szewerenko , Julian Partridge , Ron Orris
发明人： Leland Szewerenko , Julian Partridge , Ron Orris
IPC分类号： G06K9/00
CPC分类号： H01L23/4985 , H01L23/3128 , H01L23/3135 , H01L23/315 , H01L2924/0002 , H01L2924/00
摘要： Impact resistant circuit modules are disclosed for enclosing a die having a sensor area. Preferred modules include a flexible circuit and a die coupled thereto. The flexible circuit is preferably folded over compressible material to help absorb applied forces. A gap may be provided between sides of the die and the compressible material to help prevent peeling. A metal reinforcing layer may be bonded to the back of the die. A low modulus material including a patterned gap underneath the die may be used to absorb forces. A dry film adhesive may be placed between at least part of the upper surface of the die and the flexible circuit, preferably to provide further point impact resistance and protection. High and low modulus material may be combined in ruggedizing structures. Consumer devices employing such circuit modules are also taught, as well as module construction methods.
摘要翻译：公开了用于封装具有传感器区域的模具的抗冲击电路模块。优选的模块包括柔性电路和与其耦合的管芯。柔性电路优选地折叠在可压缩材料上以帮助吸收施加的力。可以在模具的侧面和可压缩材料之间提供间隙以帮助防止剥离。金属加强层可以结合到模具的背面。可以使用包括在模具下面的图案化间隙的低模量材料来吸收力。可以将干膜粘合剂放置在模具的上表面的至少一部分和柔性电路之间，优选地提供进一步的点冲击强度和保护。高和低模量材料可以结合在加固结构中。还教授了采用这种电路模块的消费者设备，以及模块构造方法。

30. 发明授权

US07371609B2 Stacked module systems and methods 有权
标题翻译：堆叠模块系统和方法
公开(公告)号：US07371609B2
公开(公告)日：2008-05-13
申请号：US10836855
申请日：2004-04-30
申请人： Julian Partridge , James Douglas Wehrly, Jr.
发明人： Julian Partridge , James Douglas Wehrly, Jr.
IPC分类号： H01L21/00
CPC分类号： H01L23/3114 , H01L23/13 , H01L23/36 , H01L23/49816 , H01L23/4985 , H01L23/5387 , H01L25/105 , H01L2224/16237 , H01L2224/32225 , H01L2224/73253 , H01L2225/107 , H01L2225/1094 , H01L2924/01327 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2924/00
摘要： The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a preferred embodiment in accordance with the invention, a form standard associated with one or more CSPs provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the contacts of the lower CSP will be compressed before flex circuitry is attached to a combination of the CSP and a form standard to create lower profile contacts between CSP and the flex circuitry.
摘要翻译：本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。在根据本发明的优选实施例中，与一个或多个CSP相关联的形式标准提供了一种物理形式，其允许在广泛的CSP包装系列中发现的许多变化的包装尺寸被利用，同时使用标准连接柔性电路设计。在优选实施例中，在CSP和形式标准的组合连接到柔性电路之前，下CSP的触点将被压缩，以在CSP和柔性电路之间形成下部轮廓接触。

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