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21. 发明授权

US06190962B1 Method of fabricating capacitor 失效
标题翻译：制造电容器的方法
公开(公告)号：US06190962B1
公开(公告)日：2001-02-20
申请号：US09467590
申请日：1999-12-20
申请人： Anchor Chen , Jing-Horng Gau
发明人： Anchor Chen , Jing-Horng Gau
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L27/10852 , H01L28/84
摘要： A fabrication method for a capacitor is proposed, beginning with a semiconductor substrate having a bit line and a planarized first dielectric layer formed thereon. A first silicon nitride layer is formed on the first dielectric layer, followed by forming in sequence a second dielectric layer and a second silicon nitride layer on the first silicon nitride layer. A photolithography and etching process is performed to form an opening in the second dielectric layer and the second silicon nitride layer. A conducting spacer is formed on a sidewall of the opening. With the spacer serving as a mask, the first silicon nitride layer and the first dielectric layer are etched to form a terminal contact opening. A conducting layer is then formed to cover the second silicon nitride layer and to fill the terminal contact opening, while the conducting layer on the second silicon nitride layer is removed by etching back. The second silicon nitride layer and the second dielectric layer are removed to expose a part of the conducting layer. A hemispherical grain layer is coated on the exposed surface of the conducting layer to complete manufacture of a lower electrode, while the lower electrode is covered by a dielectric film and an upper electrode to complete manufacture of the capacitor.
摘要翻译：提出了一种用于电容器的制造方法，从形成有位线和平坦化的第一介电层的半导体衬底开始。在第一介电层上形成第一氮化硅层，然后依次在第一氮化硅层上形成第二介电层和第二氮化硅层。进行光刻和蚀刻工艺以在第二介电层和第二氮化硅层中形成开口。导电间隔件形成在开口的侧壁上。利用间隔物作为掩模，蚀刻第一氮化硅层和第一介电层以形成端子接触开口。然后形成导电层以覆盖第二氮化硅层并填充端子接触开口，同时通过蚀刻去除第二氮化硅层上的导电层。去除第二氮化硅层和第二介电层以暴露导电层的一部分。半导体晶粒层涂覆在导电层的暴露表面上以完成下电极的制造，而下电极被电介质膜和上电极覆盖以完成电容器的制造。

22. 发明申请

US20050224917A1 Junction diode 审中-公开
标题翻译：结二极管
公开(公告)号：US20050224917A1
公开(公告)日：2005-10-13
申请号：US10823244
申请日：2004-04-12
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L27/02 , H01L27/08 , H01L29/861 , H01L31/072
CPC分类号： H01L27/0255 , H01L27/0814 , H01L29/8611
摘要： A junction diode comprising a first conductive type substrate, a second conductive type embedded region, a second conductive type well, a first conductive type doped region and a second conductive type doped region is provided. The second conductive type embedded region is formed within the first conductive type substrate. The second conductive type well is formed within the second conductive type embedded region. The concentration of dopants in the second conductive type well is smaller than the concentration of dopants in the second conductive type embedded region. The first conductive type doped region is formed in the second conductive type well. The second conductive type doped region is formed in the second conductive type embedded region. The junction diode has a smaller capacitance serves as an electrostatic discharge protection device for a radio frequency (RF) circuit without adversely affecting the transmission rate of the RF circuit.
摘要翻译：提供了包括第一导电类型衬底，第二导电类型嵌入区域，第二导电类型阱，第一导电类型掺杂区域和第二导电类型掺杂区域的结二极管。第二导电型嵌入区域形成在第一导电型衬底内。第二导电型阱形成在第二导电型嵌入区域内。第二导电型阱中的掺杂剂的浓度小于第二导电型嵌入区域中的掺杂剂的浓度。第一导电型掺杂区形成在第二导电型阱中。第二导电型掺杂区域形成在第二导电型嵌入区域中。结二极管具有较小的电容，用作射频（RF）电路的静电放电保护装置，而不会不利地影响RF电路的传输速率。

23. 发明授权

US06905935B1 Method for fabricating a vertical bipolar junction transistor 有权
标题翻译：用于制造垂直双极结型晶体管的方法
公开(公告)号：US06905935B1
公开(公告)日：2005-06-14
申请号：US10707260
申请日：2003-12-02
申请人： Jing-Horng Gau , Anchor Chen
发明人： Jing-Horng Gau , Anchor Chen
IPC分类号： H01L21/331 , H01L29/08 , H01L29/732
CPC分类号： H01L29/66272 , H01L29/0804 , H01L29/0821 , H01L29/7322
摘要： A semiconductor wafer includes a first doping region of a first conductivity type, a second doping region of a second conductivity type, and a plurality of isolated structures positioned on surfaces of the first doping region and the second doping region. A third doping region of the first conductivity type is formed in an upper portion of the second doping region. A shielding layer is formed and a portion of the shielding layer is removed to form an opening shielding layer to expose a portion of the third doping region. Subsequently, a doping layer of the second conductivity type is formed on a surface of the third doping region. A self-aligned silicidation process is performed to form a silicide layer on the surfaces of the second doping region, the third doping region and the doping layer, the silicide layer functioning as a contact region of a vertical bipolar junction transistor.
摘要翻译：半导体晶片包括第一导电类型的第一掺杂区域，第二导电类型的第二掺杂区域和位于第一掺杂区域和第二掺杂区域的表面上的多个隔离结构。第一导电类型的第三掺杂区形成在第二掺杂区的上部。形成屏蔽层，并且去除屏蔽层的一部分以形成露出第三掺杂区域的一部分的开口屏蔽层。随后，在第三掺杂区的表面上形成第二导电类型的掺杂层。执行自对准硅化工艺以在第二掺杂区域，第三掺杂区域和掺杂层的表面上形成硅化物层，硅化物层用作垂直双极结型晶体管的接触区域。

24. 发明申请

US20050118772A1 METHOD FOR FABRICATING A VERTICAL BIPOLAR JUNCTION TRANSISTOR 有权
标题翻译：用于制造垂直双极晶体管晶体管的方法
公开(公告)号：US20050118772A1
公开(公告)日：2005-06-02
申请号：US10707260
申请日：2003-12-02
申请人： Jing-Horng Gau , Anchor Chen
发明人： Jing-Horng Gau , Anchor Chen
IPC分类号： H01L21/331 , H01L29/08 , H01L29/732
CPC分类号： H01L29/66272 , H01L29/0804 , H01L29/0821 , H01L29/7322
摘要： A semiconductor wafer includes a first doping region of a first conductivity type, a second doping region of a second conductivity type, and a plurality of isolated structures positioned on surfaces of the first doping region and the second doping region. A third doping region of the first conductivity type is formed in an upper portion of the second doping region. A shielding layer is formed and a portion of the shielding layer is removed to form an opening shielding layer to expose a portion of the third doping region. Subsequently, a doping layer of the second conductivity type is formed on a surface of the third doping region. A self-aligned silicidation process is performed to form a silicide layer on the surfaces of the second doping region, the third doping region and the doping layer, the silicide layer functioning as a contact region of a vertical bipolar junction transistor.
摘要翻译：半导体晶片包括第一导电类型的第一掺杂区域，第二导电类型的第二掺杂区域和位于第一掺杂区域和第二掺杂区域的表面上的多个隔离结构。第一导电类型的第三掺杂区形成在第二掺杂区的上部。形成屏蔽层，并且去除屏蔽层的一部分以形成露出第三掺杂区域的一部分的开口屏蔽层。随后，在第三掺杂区的表面上形成第二导电类型的掺杂层。执行自对准硅化工艺以在第二掺杂区域，第三掺杂区域和掺杂层的表面上形成硅化物层，硅化物层用作垂直双极结型晶体管的接触区域。

25. 发明申请

US20050116276A1 Metal-insulator-metal (MIM) capacitor and fabrication method for making the same 审中-公开
公开(公告)号：US20050116276A1
公开(公告)日：2005-06-02
申请号：US10707225
申请日：2003-11-28
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L21/02 , H01L21/20 , H01L21/8234 , H01L21/8242 , H01L21/8244 , H01L23/522 , H01L27/108
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor includes a first metal plate; a first capacitor dielectric layer disposed on the first metal plate and a second metal plate stacked on the first capacitor dielectric layer. The first metal plate, the first capacitor dielectric layer, and the second metal plate constitute a lower capacitor. A second capacitor dielectric layer is disposed on the second metal plate. A third metal plate is stacked on the second capacitor dielectric layer. The second metal plate, the second capacitor dielectric layer, and the third metal plate constitute an upper capacitor. The first metal plate and the third metal plate are electrically connected to a first terminal of the MIM capacitor, while the second metal plate is electrically connected to a second terminal of the MIM capacitor.

26. 发明授权

US06670695B1 Method of manufacturing anti-reflection layer 有权
公开(公告)号：US06670695B1
公开(公告)日：2003-12-30
申请号：US09515811
申请日：2000-02-29
申请人： Jing-Horng Gau , Shuenn-Jeng Chen
发明人： Jing-Horng Gau , Shuenn-Jeng Chen
IPC分类号： H01L2358
CPC分类号： H01L21/0276 , G03F7/091 , H01L21/3145
摘要： An anti-reflection layer and method of manufacture. A silicon substrate has a conductive layer formed thereon. Plasma-enhanced chemical vapor deposition is performed to form a graded silicon oxynitride layer over the conductive layer. During silicon oxynitride deposition, concentration of one of the reactive gases nitrous oxide is gradually reduced so that the graded silicon oxynitride layer is oxygen-rich near bottom but nitrogen-rich near the top.

27. 发明授权

US06255168B1 Method for manufacturing bit line and bit line contact 失效
标题翻译：生产位线和位线接触的方法
公开(公告)号：US06255168B1
公开(公告)日：2001-07-03
申请号：US09394637
申请日：1999-09-13
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L21336
CPC分类号： H01L27/10885 , H01L21/76802 , H01L21/76831 , H01L21/76877 , H01L27/10888
摘要： A method for manufacturing a bit line and a bit line contact. A semiconductor substrate having a word line thereon is provided. Oxide spacers are formed on the sidewalls of the word line. A dielectric layer that covers the word line is formed over the entire substrate. A cap layer is next formed over the dielectric layer. The cap layer and the dielectric layer are patterned to form a trench in the dielectric layer. Silicon nitride spacers are formed on the sidewalls of the trench. In the subsequent step, the dielectric layer is etched down the trench to form a contact window that exposes a portion of the substrate. Polysilicon material is deposited into the contact window to form a polysilicon plug, and then metal silicide material is deposited into the trench above the plug to form a metal silicide layer.
摘要翻译：一种用于制造位线和位线接触的方法。提供其上具有字线的半导体基板。氧化物间隔物形成在字线的侧壁上。在整个基板上形成覆盖字线的电介质层。接下来在电介质层上形成覆盖层。将盖层和电介质层图案化以在电介质层中形成沟槽。氮化硅间隔物形成在沟槽的侧壁上。在随后的步骤中，电介质层沿沟槽被蚀刻以形成暴露基板的一部分的接触窗口。将多晶硅材料沉积到接触窗中以形成多晶硅塞，然后将金属硅化物材料沉积到插塞上方的沟槽中以形成金属硅化物层。

28. 发明授权

US06187649B1 Shallow trench isolation process 失效
标题翻译：浅沟槽隔离工艺
公开(公告)号：US06187649B1
公开(公告)日：2001-02-13
申请号：US09348409
申请日：1999-07-07
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L217621
CPC分类号： H01L21/76224
摘要： A shallow trench isolation process is described. A pad oxide layer is formed over a substrate. A silicon nitride layer is formed over the pad oxide layer. The silicon nitride layer is patterned. The pad oxide layer and the substrate are etched using the patterned silicon nitride as an etching mask, and thus a trench is formed in the substrate. A liner oxide layer is grown over the trench. An oxide layer is deposited to fill the trench in the substrate and has a surface level higher than the silicon nitride layer. The oxide layer is polished to partially remove the oxide layer over the silicon nitride layer. The silicon nitride layer is removed from the substrate, by which removal the oxide layer has an exposed sidewall. A polysilicon spacer is formed on the exposed sidewall. The pad oxide layer is removed. The polysilicon spacer is oxidized and transformed into an oxide spacer.
摘要翻译：描述了浅沟槽隔离工艺。在衬底上形成衬垫氧化物层。在衬垫氧化物层上形成氮化硅层。图案化氮化硅层。使用图案化的氮化硅作为蚀刻掩模蚀刻焊盘氧化物层和衬底，因此在衬底中形成沟槽。在沟槽上生长衬里氧化物层。沉积氧化物层以填充衬底中的沟槽并且具有高于氮化硅层的表面水平。抛光氧化物层以部分去除氮化硅层上的氧化物层。从衬底去除氮化硅层，通过该氮化硅去除氧化物层具有暴露的侧壁。在暴露的侧壁上形成多晶硅间隔物。去除衬垫氧化物层。将多晶硅间隔物氧化并转变为氧化物间隔物。

29. 发明授权

US6071804A Method of fabricating bit lines by damascene 有权
标题翻译：通过大马士革制造位线的方法
公开(公告)号：US6071804A
公开(公告)日：2000-06-06
申请号：US206112
申请日：1998-12-04
申请人： Jing-Horng Gau
发明人： Jing-Horng Gau
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8242 , H01L21/4763
CPC分类号： H01L27/10885 , H01L21/76802 , H01L21/76897 , H01L27/10888
摘要： A method of fabricating bit lines by damascene. A substrate having a first dielectric layer is provided, and a bit line contact is formed within the first dielectric layer. A hard material layer is formed on the first dielectric layer to expose the bit line contact. A second dielectric layer is formed on the hard material layer. An opening and a trench are formed within the second dielectric layer to expose the bit line contact and the hard material layer. A hard material spacer is formed on the sidewall of the opening and the trench. A tungsten silicide layer fills the opening and the trench to serve as a bit line on the bit line contact and an interconnect of the bit line.
摘要翻译：一种通过大马士革制造位线的方法。提供具有第一电介质层的衬底，并且在第一介电层内形成位线接触。在第一电介质层上形成硬质材料层以暴露位线接触。第二电介质层形成在硬质材料层上。在第二电介质层内形成开口和沟槽以暴露位线接触和硬质材料层。在开口和沟槽的侧壁上形成硬质材料间隔物。硅化钨层填充开口和沟槽以用作位线触点上的位线和位线的互连。

30. 发明授权

US07157766B2 Variable capactor structure and method of manufacture 有权
标题翻译：可变式压盖机结构及制造方法
公开(公告)号：US07157766B2
公开(公告)日：2007-01-02
申请号：US10921457
申请日：2004-08-18
申请人： Jing-Horng Gau , Anchor Chen
发明人： Jing-Horng Gau , Anchor Chen
IPC分类号： H01L27/108
CPC分类号： H01L27/0808
摘要： A variable capacitor comprising a substrate having a first type ion-doped buried layer, a first type ion-doped well, a second type ion-doped region and a conductive layer thereon. The first type ion-doped well is formed within the substrate. The first type ion-doped well has a cavity. The first type ion-doped buried layer is in the substrate underneath the first type ion-doped well. The first type ion-doped buried layer and the first type ion-doped well are connected. The second type ion-doped region is at the bottom of the cavity of the first type ion-doped well. The conductive layer is above and in connection with the first type ion-doped buried layer.
摘要翻译：一种可变电容器，包括具有第一类型离子掺杂掩埋层，第一类型离子掺杂阱，第二类型离子掺杂区和其上的导电层的衬底。在衬底内形成第一种类型的离子掺杂阱。第一种类型的离子掺杂阱具有空腔。第一类离子掺杂掩埋层位于第一类离子掺杂阱下的衬底中。连接第一种离子掺杂掩埋层和第一种离子掺杂阱。第二类离子掺杂区位于第一类型离子掺杂阱的空腔的底部。导电层位于第一类型的离子掺杂掩埋层之上并与之连接。

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