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21. 发明授权

US09176735B2 Digital signal processor having instruction set with one or more non-linear complex functions 有权
标题翻译：具有具有一个或多个非线性复合函数的指令集的数字信号处理器
公开(公告)号：US09176735B2
公开(公告)日：2015-11-03
申请号：US12324926
申请日：2008-11-28
申请人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
发明人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
IPC分类号： G06F7/483 , G06F9/30 , G06F17/16
CPC分类号： G06F9/3001
摘要： Methods and apparatus are provided for a digital signal processor having an instruction set with one or more non-linear complex functions. A method is provided for a processor. One or more non-linear complex software instructions are obtained from a program. The non-linear complex software instructions have at least one complex number as an input. One or more non-linear complex functions are applied from a predefined instruction set to the at least one complex number. An output is generated comprised of one complex number or two real numbers. A functional unit can implement the one or more non-linear complex functions. In one embodiment, a vector-based digital signal processor is disclosed that processes a complex vector comprised of a plurality of complex numbers. The processor can process the plurality of complex numbers in parallel.
摘要翻译：为具有具有一个或多个非线性复合函数的指令集的数字信号处理器提供了方法和装置。为处理器提供了一种方法。从程序获得一个或多个非线性复杂软件指令。非线性复杂软件指令具有至少一个复数作为输入。一个或多个非线性复函数从预定义的指令集应用到至少一个复数。产生由一个复数或两个实数组成的输出。功能单元可以实现一个或多个非线性复合函数。在一个实施例中，公开了一种处理由多个复数组成的复矢量的基于矢量的数字信号处理器。处理器可以并行处理多个复数。

22. 发明授权

US09128790B2 Digital signal processor having instruction set with an exponential function using reduced look-up table 有权
标题翻译：数字信号处理器具有使用缩减查找表的具有指数函数的指令集
公开(公告)号：US09128790B2
公开(公告)日：2015-09-08
申请号：US12362879
申请日：2009-01-30
申请人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
发明人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
IPC分类号： G06F1/035 , G06F7/556
CPC分类号： G06F7/556 , G06F1/035 , G06F2101/10
摘要： A digital signal processor is provided having an instruction set with an exponential function that uses a reduced look-up table. The disclosed digital signal processor evaluates an exponential function for an input value, x, by decomposing the input value, x, to an integer part, N, a first fractional part, q1, larger than a specified value, x0, and a second fractional part, q2, smaller than the specified value, x0; computing 2q2 using a polynomial approximation, such as a cubic approximation; obtaining 2q1 from a look-up table; and evaluating the exponential function for the input value, x, by multiplying 2q2, 2q1 and 2N together. Look-up table entries have a fewer number of bits than a number of bits in the input value, x.
摘要翻译：提供了一种数字信号处理器，其具有使用缩减的查找表的具有指数函数的指令集。所公开的数字信号处理器通过将输入值x分解为整数部分N来估算输入值x的指数函数，N，大于指定值x0的第一小数部分q1，以及第二分数部分，q2，小于指定值x0; 使用多项式近似计算2q2，例如立方近似; 从查表中获得2q1; 并且通过将2q2,2q1和2N相乘来估计输入值x的指数函数。查找表条目具有比输入值x中的位数少的位数。

23. 发明授权

US09069686B2 Digital signal processor having instruction set with one or more non-linear functions using reduced look-up table with exponentially varying step-size 有权
标题翻译：数字信号处理器具有使用具有指数变化的步长的缩小查找表的具有一个或多个非线性函数的指令集
公开(公告)号：US09069686B2
公开(公告)日：2015-06-30
申请号：US12324931
申请日：2008-11-28
申请人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
发明人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
IPC分类号： G06F17/17 , G06F17/10 , G06F1/035 , G06F9/30 , G06F9/38
CPC分类号： G06F17/10 , G06F1/035 , G06F9/3001 , G06F9/383
摘要： A digital signal processor and method are disclosed having an instruction set with one or more non-linear functions using a look-up table of reduced size and exponentially varying step-sizes. A digital signal processor evaluates a non-linear function for a value, x, by obtaining at least two values from at least one look-up table for the non-linear function that are near the value, x, wherein the at least one look-up table stores a subset of values for the non-linear function using exponentially-varying step sizes; and interpolating the at least two obtained values to obtain a result, y. A position of a leading zero in the value, x, can be used as an index into the at least one look-up table. The interpolation can comprise, for example, a linear interpolation or a polynomial interpolation. A modulo arithmetic operation can optionally be employed for a periodic non-linear function.
摘要翻译：公开了一种数字信号处理器和方法，其具有使用减小尺寸和指数级变化的步长的查找表的具有一个或多个非线性函数的指令集。数字信号处理器通过从近似于值x的非线性函数的至少一个查找表中获得至少两个值来评估值x的非线性函数，其中至少一个外观 -up表使用指数变化的步长存储用于非线性函数的值的子集; 并且内插所述至少两个获得的值以获得结果y。值x中的前导零的位置可以用作至少一个查找表中的索引。内插可以包括例如线性内插或多项式插值。对于周期性非线性函数可以可选地使用模运算。

24. 发明授权

US09069685B2 Digital signal processor having instruction set with one or more non-linear functions using reduced look-up table 有权
标题翻译：具有使用缩减查找表的具有一个或多个非线性函数的指令集的数字信号处理器
公开(公告)号：US09069685B2
公开(公告)日：2015-06-30
申请号：US12324927
申请日：2008-11-28
申请人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
发明人： Kameran Azadet , Jian-Guo Chen , Samer Hijazi , Joseph Williams
IPC分类号： G06F17/17 , G06F17/10 , G06F1/035 , G06F9/30 , G06F9/38
CPC分类号： G06F17/10 , G06F1/035 , G06F9/3001 , G06F9/383
摘要： A digital signal processor and method are disclosed having an instruction set with one or more non-linear functions using a look-up table of reduced size. A digital signal processor evaluates a non-linear function for a value, x, by obtaining two or more values for the non-linear function that are near the value, x, from at least one look-up table, wherein the at least one look-up table stores a subset of values for the non-linear function; and interpolating the two or more obtained values to obtain a result, y. The interpolation may comprise, for example, a linear interpolation or a polynomial interpolation. In a further variation, a modulo arithmetic operation can be employed for a periodic non-linear function.
摘要翻译：公开了一种使用具有缩小尺寸的查找表的具有一个或多个非线性函数的指令集的数字信号处理器和方法。数字信号处理器通过从至少一个查找表获得接近值x的非线性函数的两个或更多个值来评估值x的非线性函数，其中至少一个查找表存储非线性函数的值的子集; 并且内插两个或更多获得的值以获得结果y。插值可以包括例如线性内插或多项式插值。在另一变型中，可以对周期性非线性函数采用模运算。

25. 发明授权

US07739421B1 Buffer management method and system with data displayed directly from buffers 失效
标题翻译：缓冲区管理方法和数据直接从缓冲区显示
公开(公告)号：US07739421B1
公开(公告)日：2010-06-15
申请号：US11539440
申请日：2006-10-06
申请人： Ambalavanar Arulambalam , Jian-Guo Chen , Nevin C. Heintze , Qian Gao Xu , Jun Chao Zhao
发明人： Ambalavanar Arulambalam , Jian-Guo Chen , Nevin C. Heintze , Qian Gao Xu , Jun Chao Zhao
IPC分类号： G06F3/00 , G06F13/36
CPC分类号： G06F5/06 , G06F2205/064 , G11B20/10527 , G11B27/005 , G11B2020/10629 , G11B2020/10638 , G11B2020/10731 , G11B2020/10962 , H04L47/10 , H04L47/29 , H04L49/90 , H04L49/9047
摘要： A method includes storing video data in a disk by way of a first queue comprising a linked list of buffers. Video data are received into the first queue by way of a tail buffer. The tail buffer is at one end of the linked list of buffers in the first queue. Video data are copied from a head buffer to the disk. The head buffer is at another end of the linked list of buffers in the first queue. The video data are displayed in real-time directly from the buffers in the queue, without retrieving the displayed video data from the disk, and without interrupting the storing step.
摘要翻译：一种方法包括通过包括缓冲器的链接列表的第一队列将视频数据存储在盘中。视频数据通过尾部缓冲区被接收到第一个队列中。尾部缓冲区位于第一个队列中缓冲区的链接列表的一端。视频数据从头缓冲区复制到磁盘。头缓冲区位于第一个队列中的缓冲区的链表的另一端。视频数据直接从队列中的缓冲器中实时显示，而不从盘中检索显示的视频数据，而不会中断存储步骤。

26. 发明授权

US07599364B2 Configurable network connection address forming hardware 失效
标题翻译：可配置网络连接地址形成硬件
公开(公告)号：US07599364B2
公开(公告)日：2009-10-06
申请号：US11226507
申请日：2005-09-13
申请人： Jian-Guo Chen , Nevin C. Heintze , Hakan I. Pekcan , Cheng Gang Duan , Kent E. Wires , Lin Hua
发明人： Jian-Guo Chen , Nevin C. Heintze , Hakan I. Pekcan , Cheng Gang Duan , Kent E. Wires , Lin Hua
IPC分类号： H04L12/28 , H04L12/56 , H04J3/16 , H04J3/22 , H04J3/24 , G06F15/16
CPC分类号： H04L69/22
摘要： An apparatus and method are provided for extracting connection information from a traffic header in a communications network. The apparatus includes a first storage element containing a first look-up table for determining a first data packet header offset and data size for extracting a communications protocol type from the header and a second storage element containing a second look-up table for determining from the communications protocol type a second data packet header offset and second data size for extracting a connection address from the header. The storage elements may be in the form of content-addressable memories. Exception handling and hardware initialization can be controlled by a system processor.
摘要翻译：提供了一种用于从通信网络中的业务报头提取连接信息的装置和方法。该装置包括第一存储元件，该第一存储元件包含用于确定第一数据包标题偏移的第一查找表和用于从标题中提取通信协议类型的数据大小，以及第二存储元件，其包含第二查找表，用于从通信协议类型为从头部提取连接地址的第二数据分组报头偏移和第二数据大小。存储元件可以是可内容寻址的存储器的形式。异常处理和硬件初始化可由系统处理器控制。

27. 发明申请

US20090147787A1 METHOD AND APPARATUS FOR RTP EGRESS STREAMING USING COMPLEMENTARY DIRECTING FILE 审中-公开
标题翻译：使用补充指导文件的RTP循环流的方法和装置
公开(公告)号：US20090147787A1
公开(公告)日：2009-06-11
申请号：US12089485
申请日：2006-10-06
申请人： Ambalavanar Arulambalam , Jian-Guo Chen , Nevin C, Heintze , Hakan I. Pekcan , Kent E. Wires
发明人： Ambalavanar Arulambalam , Jian-Guo Chen , Nevin C, Heintze , Hakan I. Pekcan , Kent E. Wires
IPC分类号： H04L12/56
CPC分类号： H04L29/06027 , H04L65/103 , H04L65/104 , H04L65/4084 , H04L65/4092 , H04L65/608 , H04L65/80 , H04L67/327 , H04N21/2383 , H04N21/4135 , H04N21/4381 , H04N21/4382 , H04N21/6437
摘要： A hardware accelerated streaming arrangement, especially for RTP real time protocol streaming, employs a directing file determining the pointers, header lengths and offsets of a block of one or more data packets to be sent out through a network accelerated streaming system. The directing file is established by a control processor, for example working in the background, and is stored to provide information making it possible to determine certain information including header sizes and pointers to RTP payload and other data, without the need during egress of the data for analysis related to the type of media or protocol concerned. This relieves the control processor of functions that would otherwise require attention, and permits the egress process to proceed in a repetitive manner, preferably relying insofar as possible on hardware elements for speed and reserving the control processors computational capacity for control functions that may be more complex but are infrequent and/or not time sensitive for streaming in real time.
摘要翻译：硬件加速流布置，特别是对于RTP实时协议流传输，采用指导文件来确定通过网络加速流传输系统发送的一个或多个数据分组的块的指针，头长度和偏移量。定向文件由控制处理器建立，例如在后台工作，并且被存储以提供信息，使得可以确定包括头部大小和指向RTP有效载荷和其他数据的指定信息，而不需要在数据出口期间用于与相关媒体或协议类型相关的分析。这将使控制处理器免除另外需要注意的功能，并允许出口过程以重复的方式进行，优选地依赖于硬件元件上的速度和保留控制处理器对于可能更复杂的控制功能的计算能力但对于实时流式传输并不频繁和/或不时间敏感。

28. 发明申请

US20080285571A1 Media Data Processing Using Distinct Elements for Streaming and Control Processes 审中-公开
标题翻译：媒体数据处理使用不同的元素进行流和控制过程
公开(公告)号：US20080285571A1
公开(公告)日：2008-11-20
申请号：US12089509
申请日：2006-10-06
申请人： Ambalavanar Arulambalam , Jian-Guo Chen , Nevin C. Heintze , Hakan I. Pekcan , Kent E. Wires
发明人： Ambalavanar Arulambalam , Jian-Guo Chen , Nevin C. Heintze , Hakan I. Pekcan , Kent E. Wires
IPC分类号： H04L12/56
CPC分类号： H04L29/06027 , H04L65/103 , H04L65/104 , H04L65/4084 , H04L65/4092 , H04L65/608 , H04L65/80 , H04L67/327 , H04N21/2383 , H04N21/4135 , H04N21/4381 , H04N21/4382 , H04N21/6437
摘要： A hardware accelerated streaming arrangement, especially for RTP real time protocol streaming, directs data packets for one or more streams between sources and destinations, using addressing and handling criteria that are determined in part from control packets and are used to alter or supplement headers associated with the stream content packets. A programmed control processor responds to control packets in RTCP or RTSP format, whereby the handling or direction of RTP packets can be changed. The control processor stores data for the new addressing and handling criteria in a memory accessible to a hardware accelerator, arranged to store the criteria for multiple ongoing streams at the same time. When a content packet is received, its addressing and handling criteria are found in the memory and applied, by action of the network accelerator, without the need for computation by the control processor. The network accelerator operates repetitively to continue to apply the criteria to the packets for a given stream as the stream continues, and can operate as a high date rate pipeline. The processor can be programmed to revise the criteria in a versatile manner, including using extensive computation if necessary, because the processor is relieved of repetitive processing duties accomplished by the network accelerator.
摘要翻译：硬件加速流布置，特别是对于RTP实时协议流传输，使用寻址和处理标准来指导源和目的地之间的一个或多个流的数据分组，这些标准部分地由控制分组确定并用于改变或补充与流内容包。编程控制处理器以RTCP或RTSP格式响应控制分组，从而可以改变RTP分组的处理或方向。控制处理器将用于新的寻址和处理标准的数据存储在硬件加速器可访问的存储器中，该存储器被布置为同时存储多个正在进行的流的标准。当接收到内容分组时，其寻址和处理标准在存储器中被发现，并且通过网络加速器的动作被应用，而不需要控制处理器的计算。当流继续时，网络加速器重复操作以继续将标准应用于给定流的分组，并且可以作为高日期速率流水线操作。处理器可以被编程为以通用方式修改标准，包括如果需要使用广泛的计算，因为处理器不受网络加速器实现的重复处理任务。

29. 发明申请

US20070058633A1 Configurable network connection address forming hardware 失效
标题翻译：可配置网络连接地址形成硬件
公开(公告)号：US20070058633A1
公开(公告)日：2007-03-15
申请号：US11226507
申请日：2005-09-13
申请人： Jian-Guo Chen , Nevin Heintze , Hakan Pekcan , Cheng Duan , Kent Wires , Lin Hua
发明人： Jian-Guo Chen , Nevin Heintze , Hakan Pekcan , Cheng Duan , Kent Wires , Lin Hua
IPC分类号： H04L12/28
CPC分类号： H04L69/22
摘要： An apparatus and method are provided for extracting connection information from a traffic header in a communications network. The apparatus includes a first storage element containing a first look-up table for determining a first data packet header offset and data size for extracting a communications protocol type from the header and a second storage element containing a second look-up table for determining from the communications protocol type a second data packet header offset and second data size for extracting a connection address from the header. The storage elements may be in the form of content-addressable memories. Exception handling and hardware initialization can be controlled by a system processor.
摘要翻译：提供了一种用于从通信网络中的业务报头提取连接信息的装置和方法。该装置包括第一存储元件，该第一存储元件包含用于确定第一数据包标题偏移的第一查找表和用于从标题中提取通信协议类型的数据大小，以及第二存储元件，其包含第二查找表，用于从通信协议类型为从头部提取连接地址的第二数据分组报头偏移和第二数据大小。存储元件可以是可内容寻址的存储器的形式。异常处理和硬件初始化可由系统处理器控制。

30. 发明授权

US06754795B2 Methods and apparatus for forming linked list queue using chunk-based structure 有权
标题翻译：使用基于块的结构形成链表的队列的方法和装置
公开(公告)号：US06754795B2
公开(公告)日：2004-06-22
申请号：US10029680
申请日：2001-12-21
申请人： Jian-Guo Chen , David E. Clune , Hanan Z. Moller , David P. Sonnier
发明人： Jian-Guo Chen , David E. Clune , Hanan Z. Moller , David P. Sonnier
IPC分类号： G06F1206
CPC分类号： G06F5/10 , G06F2205/064 , H04L49/25 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： A processing system comprises processing circuitry and memory circuitry coupled to the processing circuitry. The memory circuitry is configurable to maintain at least one queue structure representing a list of data units (e.g., pointers to packets stored in a packet memory). The queue structure is partitioned into two or more blocks (e.g., chunks) wherein at least some of the blocks of the queue structure include two or more data units. Further, at least some of the blocks of the queue structure may include a pointer to a next block of the queue structure (e.g., a next chunk pointer). Given such a queue structure, the processing circuitry is configurable to address a first block of the queue structure, and then address a next block of the queue structure by setting the next block pointer of the first block to point to the next block.
摘要翻译：处理系统包括耦合到处理电路的处理电路和存储器电路。存储器电路可配置为保持表示数据单元列表的至少一个队列结构（例如，指向存储在分组存储器中的分组的指针）。队列结构被划分为两个或更多个块（例如，块），其中队列结构的至少一些块包括两个或多个数据单元。此外，队列结构的至少一些块可以包括指向队列结构的下一个块（例如，下一个块指针）的指针。给定这种队列结构，处理电路可配置为寻址队列结构的第一块，然后通过将第一块的下一个块指针设置为指向下一个块来寻址队列结构的下一个块。

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