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21. 发明授权

US07337415B2 Systematic yield in semiconductor manufacture 有权
标题翻译：半导体制造系统产量
公开(公告)号：US07337415B2
公开(公告)日：2008-02-26
申请号：US10711978
申请日：2004-10-18
申请人： Paul H. Bergeron , Jason D. Hibbeler , Gustavo E. Tellez
发明人： Paul H. Bergeron , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, design changes are performed to make structures more likely to function, either by forming a more planar surface on the lower layer or by compensating in the upper layer for the lack of planarity. The changes to improve manufacturing yield are made at the design stage rather than at the fabrication stage.
摘要翻译：提供三维结构，其提高半导体器件中某些结构的制造成品率。三维结构考虑到上层和下层之间的相互作用，其中下层由于其设计而具有形成非平面表面的倾向。因此，通过在下层上形成更平坦的表面或者通过在上层补偿缺乏平面性，进行设计变更以使结构更有可能起作用。提高制造产量的变化是在设计阶段而不是在制造阶段进行的。

22. 发明授权

US07120887B2 Cloned and original circuit shape merging 失效
标题翻译：克隆和原始电路形状合并
公开(公告)号：US07120887B2
公开(公告)日：2006-10-10
申请号：US10707845
申请日：2004-01-16
申请人： Henry A. Bonges, III , Michael S. Gray , Jason D. Hibbeler , Kevin W. McCullen , Robert F. Walker
发明人： Henry A. Bonges, III , Michael S. Gray , Jason D. Hibbeler , Kevin W. McCullen , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, system and program product for merging cloned and original circuit shapes such that a union thereof does not include a notch. The invention determines, for a cell including an original circuit shape and at least one overlapping clone of the original circuit shape, whether each clone corner point of each overlapping clone is within a threshold distance of a corresponding original corner point of the original circuit shape; and generates, in the case that each clone corner point of each overlapping clone circuit shape is within a threshold distance, a union of each overlapping clone and the original circuit shape such that the union does not contain a notch. The union is generated using a point code that sets a new position for a union corner point to remove a notch based on the original shape's direction and the edge orientations previous to and next to the corner point.
摘要翻译：用于合并克隆和原始电路形状的方法，系统和程序产品，使得其联合不包括缺口。本发明对于包括原始电路形状的单元和原始电路形状的至少一个重叠克隆来确定每个重叠克隆的每个克隆角点是否处于原始电路形状的相应原始角点的阈值距离内; 并且在每个重叠克隆电路形状的每个克隆角点处于阈值距离内的情况下，生成每个重叠克隆的结合和原始电路形状，使得联合不包含凹口。联合是使用点代码生成的，该点代码为联合角点设置新位置，以根据原始形状的方向和角点之前和之后的边缘方向去除凹口。

23. 发明授权

US07093234B2 Dynamic CPU usage profiling and function call tracing 失效
公开(公告)号：US07093234B2
公开(公告)日：2006-08-15
申请号：US09939005
申请日：2001-08-24
申请人： Jason D. Hibbeler , Jhy-Chun Wang
发明人： Jason D. Hibbeler , Jhy-Chun Wang
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F11/3466 , G06F11/3423 , G06F2201/865
摘要： A method, and computer readable medium for the dynamic CPU (Central Processing Unit) usage and function call tracing on a target application. The setup of the tracing uses a -pg like solution, and is implemented using the DPCL (Dynamic Probe Class Library). The output is presented in a gmon.out format, which allows the use of popular analysis tools. The program being traced need not be recompiled or re-linked. This is particularly important if the source code is not available. The dynamic feature allows for different choices of profiling and the choice can even be changed once the target application is running.

24. 发明授权

US08418090B2 Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool 失效
公开(公告)号：US08418090B2
公开(公告)日：2013-04-09
申请号：US13368413
申请日：2012-02-08
申请人： Jeanne P. Bickford , Jason D. Hibbeler , Juergen Koehl
发明人： Jeanne P. Bickford , Jason D. Hibbeler , Juergen Koehl
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed. The fault density value is subsequently compared to a predetermined value, wherein the predetermined value is determined using test structures and/or yield data from a target manufacturing process.

25. 发明授权

US08136066B2 Apparatus and computer program product for semiconductor yield estimation 有权
标题翻译：用于半导体产量估算的装置和计算机程序产品
公开(公告)号：US08136066B2
公开(公告)日：2012-03-13
申请号：US12325774
申请日：2008-12-01
申请人： Jeanne Paulette Spence Bickford , Jason D. Hibbeler , Juergen Koehl , William John Livingstone , Daniel Nelson Maynard
发明人： Jeanne Paulette Spence Bickford , Jason D. Hibbeler , Juergen Koehl , William John Livingstone , Daniel Nelson Maynard
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method, apparatus, system, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.
摘要翻译：一种方法，装置，系统和计算机程序产品，其使用具有冗余和非冗余元件的集成电路上的关键区域分析来执行产量估计。非冗余元素将被忽略或从对不需要的打开执行的关键区域分析中移除。

26. 发明授权

US08010916B2 Test yield estimate for semiconductor products created from a library 有权
标题翻译：从图书馆创建的半导体产品的测试产量估算
公开(公告)号：US08010916B2
公开(公告)日：2011-08-30
申请号：US12062586
申请日：2008-04-04
申请人： Jeanne Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl
发明人： Jeanne Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield impact of combining these library elements. For example, the method considers the test yield impact of sensitivity to library element to library element shorts and the test yield impact of sensitivity to wiring faults. The disclosed method further allows die size growth to be traded off against the use of library elements with higher test yield in order to provide an optimal design solution. Thus, the method may be used to modify library element selection so as to optimize test yield. Lastly, the method further repeats itself at key design checkpoints to revalidate initial test yield (and cost) assumptions made when the product was quoted to a customer. Thus, the method provides increased accuracy of test yield estimate from initial sizing through design and further allows designs to be modified to improve test yield.
摘要翻译：公开了一种在设计布局之前预测半导体产品的测试产量的方法。这是通过对用于形成特定产品的单个库元素应用关键区域分析，并通过估计组合这些库元素的测试产出影响来实现的。例如，该方法考虑了库元素对库元素短路的灵敏度的测试产量影响以及对接线故障的灵敏度的测试产量影响。所公开的方法进一步允许模具尺寸增长与使用具有较高测试成品率的库元件进行交易，以便提供最佳设计解决方案。因此，该方法可用于修改库元素选择以优化测试产量。最后，该方法在关键设计检查点进一步重复，以重新验证产品被引用给客户时的初始测试收益（和成本）假设。因此，该方法通过设计从初始尺寸提高了测试产量估算的准确度，并进一步允许修改设计以提高测试产量。

27. 发明授权

US07960836B2 Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same 有权
标题翻译：冗余微环结构用于集成电路物理设计过程及其形成方法
公开(公告)号：US07960836B2
公开(公告)日：2011-06-14
申请号：US12045374
申请日：2008-03-10
申请人： Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
发明人： Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
IPC分类号： H01L23/52
CPC分类号： H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and Fourth wires form a path between the first and second wires redundant to the first via.
摘要翻译：一种集成电路，包括第一级布线轨道的第一线，第二级布线轨道的第二线，第三级布线轨道的第三线和与第二线的第一距离的第四线第二层线路。第一通孔在第二导线的第一位置连接第一和第二导线。第二通孔在第一位置处连接第二和第三导线，第二通孔基本上与第一通孔轴向对准。第三通过在第四线的第二位置连接第三和第四导线。第四通孔在第二位置处连接第一和第四导线，第四通孔基本上与第三通孔轴向对准。第二，第三和第四通孔以及第三和第四导线形成第一和第二导线之间的路径，该路径对于第一通孔是冗余的。

28. 发明申请

US20110088008A1 METHOD FOR CONVERSION OF COMMERCIAL MICROPROCESSOR TO RADIATION-HARDENED PROCESSOR AND RESULTING PROCESSOR 审中-公开
标题翻译：将商业微处理器转换为辐射加工处理器和结果处理器的方法
公开(公告)号：US20110088008A1
公开(公告)日：2011-04-14
申请号：US12579159
申请日：2009-10-14
申请人： John A. FIFIELD , Mark C. HAKEY , Jason D. HIBBELER , James S. NAKOS , Tak H. NING , Kenneth P. RODBELL , Ronald D. ROSE , Henry H.K. TANG , Larry WISSEL
发明人： John A. FIFIELD , Mark C. HAKEY , Jason D. HIBBELER , James S. NAKOS , Tak H. NING , Kenneth P. RODBELL , Ronald D. ROSE , Henry H.K. TANG , Larry WISSEL
IPC分类号： G06F17/50 , H03M13/05 , G06F11/10
CPC分类号： G06F17/5068 , G06F11/1048 , G06F17/505
摘要： A method is provided to convert commercial microprocessors to radiation-hardened processors and, more particularly, a method is provided to modify a commercial microprocessor for radiation hardened applications with minimal changes to the technology, design, device, and process base so as to facilitate a rapid transition for such radiation hardened applications. The method is implemented in a computing infrastructure and includes evaluating a probability that one or more components of an existing commercial design will be affected by a single event upset (SEU). The method further includes replacing the one or more components with a component immune to the SEU to create a final device.
摘要翻译：提供了一种将商业微处理器转换为辐射硬化处理器的方法，更具体地，提供了一种方法，以便以最小的技术，设计，设备和工艺基础的改变来修改用于辐射硬化应用的商业微处理器，以便于这种辐射硬化应用的快速过渡。该方法在计算基础设施中实现，并且包括评估现有商业设计的一个或多个组件将受到单个事件不适（SEU）的影响的概率。该方法还包括用免疫SEU的成分替换一个或多个成分以产生最终的装置。

29. 发明授权

US07761821B2 Technology migration for integrated circuits with radical design restrictions 失效
标题翻译：具有激进设计限制的集成电路的技术迁移
公开(公告)号：US07761821B2
公开(公告)日：2010-07-20
申请号：US11837732
申请日：2007-08-13
申请人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。本发明实现了解决RDR要求的最小布局扰动方法。本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。

30. 发明申请

US20100023913A1 METHOD FOR IC WIRING YIELD OPTIMIZATION, INCLUDING WIRE WIDENING DURING AND AFTER ROUTING 有权
标题翻译： IC接线优化方法，包括在路由和之后的线路宽带化
公开(公告)号：US20100023913A1
公开(公告)日：2010-01-28
申请号：US12572297
申请日：2009-10-02
申请人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
发明人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.
摘要翻译：公开了用于为设计执行屈服感知IC路由的方法，服务和计算机程序产品的实施例。该方法执行满足布线拥塞约束的初始全局路由。接下来，该方法基于例如二次拥塞优化来逐层地在全局路由上执行线扩展和线拓宽。之后，使用电线扩展和线宽加工的结果，在全局路线上执行定时关闭。使用关键区域产量模型进行布线后布线宽度和布线调整。此外，该方法允许优化已经路由的数据。

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