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21. 发明授权

US09268636B2 Semiconductor memory devices including error correction circuits and methods of operating the semiconductor memory devices 有权
标题翻译：半导体存储器件包括纠错电路和操作半导体存储器件的方法
公开(公告)号：US09268636B2
公开(公告)日：2016-02-23
申请号：US13910591
申请日：2013-06-05
申请人： Hoi-ju Chung , Su-A Kim , Mu-Jin Seo , Hak-Soo Yu , Jae-Youn Youn , Hyo-Jin Choi
发明人： Hoi-ju Chung , Su-A Kim , Mu-Jin Seo , Hak-Soo Yu , Jae-Youn Youn , Hyo-Jin Choi
IPC分类号： G11C29/00 , G06F11/10
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0679 , G06F11/073 , G06F11/076 , G06F11/079 , G06F11/0793 , G06F11/1008 , G06F11/1048 , G06F11/1068 , G06F11/1076 , G11C11/409 , G11C29/52 , G11C29/783
摘要： A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.
摘要翻译：存储器控制器包括：控制器输入/输出电路，被配置为输出第一命令以读取第一数据，并输出第二命令以读取第一数据的纠错部分。存储装置包括：误差检测器，数据存储电路和纠错电路。错误检测器被配置为响应于第一命令来检测从存储器单元读取的数据中的错误位数。如果检测到的错误比特数大于或等于第一阈值，则数据存储电路被配置为存储读取数据。误差校正电路被配置为校正存储的数据。

22. 发明申请

US20150049570A1 MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, OPERATING METHOD THEREOF 审中-公开
标题翻译：存储器件，包括其的存储器系统，其操作方法
公开(公告)号：US20150049570A1
公开(公告)日：2015-02-19
申请号：US14450537
申请日：2014-08-04
申请人： Sung-Hyun LEE , Jun-Hee YOO , Dong-Soo KANG , Sua KIM , Hak-Soo YU , Jae-Youn YOUN , Hyo-Jin CHOI
发明人： Sung-Hyun LEE , Jun-Hee YOO , Dong-Soo KANG , Sua KIM , Hak-Soo YU , Jae-Youn YOUN , Hyo-Jin CHOI
IPC分类号： G11C8/08 , G11C8/10
CPC分类号： G11C8/08 , G11C7/1042 , G11C7/12 , G11C8/10
摘要： In one embodiment, the memory device includes at least one memory bank including first and second subbanks, and control logic configured to control storing data into the memory bank. The control logic is configured to activate the first subbank and to precharge the second subbank in response to a first activate command for the first subbank.
摘要翻译：在一个实施例中，存储器件包括至少一个包括第一和第二子库的存储体，以及被配置为控制将数据存储到存储体中的控制逻辑。控制逻辑被配置为响应于第一子银行的第一激活命令来激活第一子库并且预充电第二子库。

23. 发明授权

US07738311B2 Semiconductor memory devices having optimized memory block organization and data line routing for reducing chip size and increasing speed 有权
标题翻译：具有优化的存储器块组织和数据线路由的半导体存储器件，用于减小芯片尺寸和增加速度
公开(公告)号：US07738311B2
公开(公告)日：2010-06-15
申请号：US11935869
申请日：2007-11-06
申请人： Jae-Youn Youn , Sang-Jae Rehh
发明人： Jae-Youn Youn , Sang-Jae Rehh
IPC分类号： G11C7/00
CPC分类号： G11C5/063 , G11C5/025 , G11C7/10 , G11C11/4097
摘要： Multi-bank semiconductor memory devices are provided having optimized memory block layouts and data line routing to enable chip size reduction and increase operating memory access speed.
摘要翻译：提供了具有优化的存储器块布局和数据线路由以实现芯片尺寸减小和增加操作存储器访问速度的多存储体半导体存储器件。

24. 发明申请

US20100067317A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING SENSE AMPLIFIER OF SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件的控制和半导体存储器件的感测放大器的方法
公开(公告)号：US20100067317A1
公开(公告)日：2010-03-18
申请号：US12552615
申请日：2009-09-02
申请人： Sang-Hoon Jung , Jae-Youn Youn , Young-Sun Min
发明人： Sang-Hoon Jung , Jae-Youn Youn , Young-Sun Min
IPC分类号： G11C7/06 , G11C7/00
CPC分类号： G11C7/08 , G11C7/065 , G11C11/406 , G11C11/40615 , G11C11/4091 , G11C2211/4065
摘要： A semiconductor memory device includes at least one sense amplifier, a controller and a sense amplifier driver. The sense amplifier includes a PMOS sense amplifier and an NMOS sense amplifier configured to be respectively activated in response to a first supply voltage and a second supply voltage, and to sense and amplify a voltage difference between a corresponding bit line pair. The controller is configured to set an operating mode in response to an external command, to control activation timing of a PMOS drive activation signal and an NMOS drive activation signal according to the set operating mode, and to output the PMOS drive activation signal and the NMOS drive activation signal. The sense amplifier driver is configured to apply the first and second supply voltages to the PMOS and NMOS sense amplifiers, respectively, in response to the PMOS drive activation signal and the NMOS drive activation signal.
摘要翻译：半导体存储器件包括至少一个读出放大器，控制器和读出放大器驱动器。读出放大器包括PMOS读出放大器和NMOS读出放大器，其配置为分别响应于第一电源电压和第二电源电压被激活，并且检测和放大对应位线对之间的电压差。控制器被配置为响应于外部命令来设置操作模式，以根据设定的操作模式控制PMOS驱动激活信号的激活定时和NMOS驱动激活信号，并且输出PMOS驱动激活信号和NMOS 驱动启动信号。读出放大器驱动器被配置为分别响应于PMOS驱动激活信号和NMOS驱动器激活信号将第一和第二电源电压施加到PMOS和NMOS读出放大器。

25. 发明申请

US20080112251A1 SEMICONDUCTOR MEMORY DEVICES HAVING OPTIMIZED MEMORY BLOCK ORGANIZATION AND DATA LINE ROUTING FOR REDUCING CHIP SIZE AND INCREASING SPEED 有权
标题翻译：具有优化的存储器块组织和数据线路径的半导体存储器件，用于减少芯片尺寸并增加速度
公开(公告)号：US20080112251A1
公开(公告)日：2008-05-15
申请号：US11935869
申请日：2007-11-06
申请人： Jae-Youn Youn , Sang-Jae Rehh
发明人： Jae-Youn Youn , Sang-Jae Rehh
IPC分类号： G11C8/00
CPC分类号： G11C5/063 , G11C5/025 , G11C7/10 , G11C11/4097
摘要： Multi-bank semiconductor memory devices are provided having optimized memory block layouts and data line routing to enable chip size reduction and increase operating memory access speed.
摘要翻译：提供了具有优化的存储器块布局和数据线路由以实现芯片尺寸减小和增加操作存储器访问速度的多存储体半导体存储器件。

26. 发明授权

US07102936B2 Internal voltage generating circuit for periphery, semiconductor memory device having the circuit and method thereof 有权
公开(公告)号：US07102936B2
公开(公告)日：2006-09-05
申请号：US10999354
申请日：2004-11-29
申请人： Jae-Hoon Kim , Jae-Youn Youn
发明人： Jae-Hoon Kim , Jae-Youn Youn
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C11/413
摘要： An internal voltage generator for memory bank peripheral circuitry, a semiconductor memory device having the internal voltage generator, and a method for generating an internal voltage are provided. A switchable internal voltage generating circuit according to the present invention includes a control section and an internal voltage generating circuit. The control section generates a control signal in response to a bank activation command and a bank activation signal for enabling memory banks. The internal voltage generating circuit receives a reference voltage, and responds to the control signal to output an internal voltage equal to the reference voltage. The control signal is enabled when the bank activation command and the bank activation signal are concurrently enabled. The bank activation signal is generated in response to a bank address. The internal voltage can be supplied only to peripheral circuits of the banks selected by the bank address, thereby preventing unnecessary power consumption, effectively controlling the internal voltage, and always properly supplying the internal voltage.

27. 发明申请

US20050094467A1 Internal voltage generating circuit for periphery, semiconductor memory device having the circuit and method thereof 有权
公开(公告)号：US20050094467A1
公开(公告)日：2005-05-05
申请号：US10999354
申请日：2004-11-29
申请人： Jae-Hoon Kim , Jae-Youn Youn
发明人： Jae-Hoon Kim , Jae-Youn Youn
IPC分类号： G11C11/413 , G11C5/14 , G11C7/00
CPC分类号： G11C5/14 , G11C11/413
摘要： An internal voltage generator for memory bank peripheral circuitry, a semiconductor memory device having the internal voltage generator, and a method for generating an internal voltage are provided. A switchable internal voltage generating circuit according to the present invention includes a control section and an internal voltage generating circuit. The control section generates a control signal in response to a bank activation command and a bank activation signal for enabling memory banks. The internal voltage generating circuit receives a reference voltage, and responds to the control signal to output an internal voltage equal to the reference voltage. The control signal is enabled when the bank activation command and the bank activation signal are concurrently enabled. The bank activation signal is generated in response to a bank address. The internal voltage can be supplied only to peripheral circuits of the banks selected by the bank address, thereby preventing unnecessary power consumption, effectively controlling the internal voltage, and always properly supplying the internal voltage.

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