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1. 发明授权

US07501881B2 Boosting voltage generating circuit for generating a stable boosting voltage under a wider range of supply voltage and semiconductor memory device having the same 有权
标题翻译：用于在更宽的电源电压范围内产生稳定的升压电压的升压电压产生电路和具有该升压电压的半导体存储器件
公开(公告)号：US07501881B2
公开(公告)日：2009-03-10
申请号：US11707001
申请日：2007-02-16
申请人： Jae Youn Youn , Han Na Park
发明人： Jae Youn Youn , Han Na Park
IPC分类号： G05F1/10
CPC分类号： H02M3/1584 , G11C5/145 , G11C5/147 , G11C8/08
摘要： The boosting voltage generating circuit of example embodiments may include a boosting level detection unit, a first boosting pump, and a second boosting pump. The boosting level detection unit may be configured to generate a target level detection signal and a margin level detection signal. The target level detection signal may have a logic state according to a level of a boosting voltage compared with a target voltage level, and the margin level detection signal may have a logic state according to a level of the boosting voltage compared with a margin voltage level, the margin voltage level being higher than the target voltage level. The first boosting pump may be controlled based on a target voltage level. The second boosting pump may be controlled based on a margin voltage level. According to the boosting voltage generating circuit of example embodiments, overshoot of the boosting voltage by the second boosting pump may remarkably decrease. Accordingly, the boosting voltage generating circuit of example embodiments may generate a stable boosting voltage under a wider range of supply voltage.
摘要翻译：示例性实施例的升压电压产生电路可以包括升压电平检测单元，第一增压泵和第二增压泵。升压电平检测单元可以被配置为产生目标电平检测信号和余量电平检测信号。与目标电压电平相比，目标电平检测信号可以根据升压电压的电平具有逻辑状态，并且边沿电平检测信号可以根据升压电压的电平与余量电压电平相比具有逻辑状态，余量电压电平高于目标电压电平。可以基于目标电压电平来控制第一增压泵。可以基于余量电压电平来控制第二增压泵。根据示例性实施例的升压电压产生电路，第二增压泵的升压电压的过冲可能显着降低。因此，示例性实施例的升压电压产生电路可以在更宽的电源电压范围内产生稳定的升压电压。

2. 发明授权

US06842382B2 Internal voltage generating circuit for periphery, semiconductor memory device having the circuit and method thereof 失效
公开(公告)号：US06842382B2
公开(公告)日：2005-01-11
申请号：US10217799
申请日：2002-08-12
申请人： Jae-Hoon Kim , Jae-Youn Youn
发明人： Jae-Hoon Kim , Jae-Youn Youn
IPC分类号： G11C11/413 , G11C5/14 , G11C16/04
CPC分类号： G11C5/14 , G11C11/413
摘要： An internal voltage generator for memory bank peripheral circuitry, a semiconductor memory device having the internal voltage generator, and a method for generating an internal voltage are provided. A switchable internal voltage generating circuit according to the present invention includes a control section and an internal voltage generating circuit. The control section generates a control signal in response to a bank activation command and a bank activation signal for enabling memory banks. The internal voltage generating circuit receives a reference voltage, and responds to the control signal to output an internal voltage equal to the reference voltage. The control signal is enabled when the bank activation command and the bank activation signal are concurrently enabled. The bank activation signal is generated in response to a bank address. The internal voltage can be supplied only to peripheral circuits of the banks selected by the bank address, thereby preventing unnecessary power consumption, effectively controlling the internal voltage, and always properly supplying the internal voltage.

3. 发明授权

US06018485A Semiconductor memory device with cascaded burn-in test capability 有权
标题翻译：具有级联老化测试能力的半导体存储器件
公开(公告)号：US06018485A
公开(公告)日：2000-01-25
申请号：US221828
申请日：1998-12-28
申请人： Gi-Won Cha , Jae-Youn Youn
发明人： Gi-Won Cha , Jae-Youn Youn
IPC分类号： G01R31/28 , G11C29/00 , G11C29/06 , G11C29/50 , G11C7/00
CPC分类号： G11C29/50 , G11C29/006 , G11C11/401
摘要： A semiconductor memory device with a cascaded burn-in test capability for a plurality of memory cell blocks. A delayed feedback signal is communicated between memory cell block selection circuits to create the cascade burn-in.
摘要翻译：一种具有用于多个存储单元块的级联老化测试能力的半导体存储器件。在存储单元块选择电路之间传送延迟的反馈信号以产生级联老化。

4. 发明授权

US09330743B2 Memory cores of resistive type memory devices, resistive type memory devices and method of sensing data in the same 有权
标题翻译：电阻型存储器件的存储器核心，电阻型存储器件以及感测数据的方法
公开(公告)号：US09330743B2
公开(公告)日：2016-05-03
申请号：US14677991
申请日：2015-04-03
申请人： Chan-Kyung Kim , Kee-Won Kwon , Su-A Kim , Chul-Woo Park , Jae-Youn Youn
发明人： Chan-Kyung Kim , Kee-Won Kwon , Su-A Kim , Chul-Woo Park , Jae-Youn Youn
IPC分类号： G11C11/00 , G11C11/16 , G11C5/08 , G11C7/06 , G11C5/02 , G11C13/00 , G11C11/4091
CPC分类号： G11C11/16 , G11C5/025 , G11C5/08 , G11C7/065 , G11C11/161 , G11C11/1653 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/4091 , G11C13/0023 , G11C13/004 , G11C2013/0042 , G11C2213/79 , G11C2213/82
摘要： A memory core of a resistive type memory device includes at least a first resistive type memory cell coupled to a bit-line, a first resistance to voltage converter and a bit-line sense amplifier. The first resistance to voltage converter is coupled to the bit-line at a first node. The first resistance to voltage converter converts a resistance of the first resistive type memory cell to a corresponding voltage based on a read column selection signal. The bit-line sense amplifier is coupled to the bit-line at the first node and is coupled to a complementary bit-line at a second node. The bit-line sense amplifier senses and amplifies a voltage difference of the bit-line and the complementary bit-line in response to a sensing control signal.
摘要翻译：电阻型存储器件的存储核心至少包括耦合到位线的第一电阻型存储单元，第一电阻转换器和位线读出放大器。第一电阻转换器在第一节点处耦合到位线。第一电阻转换器基于读列选择信号将第一电阻型存储单元的电阻转换成相应的电压。位线读出放大器耦合到第一节点处的位线，并且耦合到第二节点处的互补位线。位线检测放大器响应于感测控制信号而感测和放大位线和互补位线的电压差。

5. 发明授权

US09076504B2 Semiconductor memory device and refresh method thereof 有权
标题翻译：半导体存储器件及其刷新方法
公开(公告)号：US09076504B2
公开(公告)日：2015-07-07
申请号：US13661773
申请日：2012-10-26
申请人： Jong-Ho Lee , Kyu-Chang Kang , Hyo-Chang Kim , Jae-Youn Youn , Sang-Jae Rhee
发明人： Jong-Ho Lee , Kyu-Chang Kang , Hyo-Chang Kim , Jae-Youn Youn , Sang-Jae Rhee
IPC分类号： G11C7/08 , G11C11/406 , G11C11/4091
CPC分类号： G11C7/08 , G11C11/40626 , G11C11/4091 , G11C2211/4065 , G11C2211/4068
摘要： A semiconductor memory device and a self-refresh method of the semiconductor memory device. The semiconductor memory device includes: a memory cell array including one or more memory cells; a sense amplifier connected to a sensing line and a complementary sensing line and sensing/amplifying data stored in the one or more memory cells; and a sense amplifier control circuit sequentially supplying a first voltage and a second voltage having different levels to the sense amplifier through the sensing line during a refresh operation.
摘要翻译：半导体存储器件和半导体存储器件的自刷新方法。半导体存储器件包括：包括一个或多个存储单元的存储单元阵列; 连接到感测线和互补感测线的感测放大器，以及感测/放大存储在所述一个或多个存储器单元中的数据; 以及读出放大器控制电路，其在刷新操作期间通过感测线路顺序地将具有不同电平的第一电压和第二电压提供给读出放大器。

6. 发明申请

US20140317469A1 MEMORY DEVICE FOR PERFORMING ERROR CORRECTION CODE OPERATION AND REDUNDANCY REPAIR OPERATION 有权
标题翻译：用于执行错误修正代码操作和冗余维修操作的存储器件
公开(公告)号：US20140317469A1
公开(公告)日：2014-10-23
申请号：US14208795
申请日：2014-03-13
申请人： Young-soo Sohn , Kwang-il Park , Chul-woo Park , Jong-pil Son , Jae-youn Youn , Hoi-ju Chung
发明人： Young-soo Sohn , Kwang-il Park , Chul-woo Park , Jong-pil Son , Jae-youn Youn , Hoi-ju Chung
IPC分类号： G06F11/10 , G11C29/10
CPC分类号： G06F11/1068 , G06F3/064 , G06F3/0679 , G06F11/1052 , G11C29/42 , G11C29/44 , G11C29/4401 , G11C29/52 , G11C29/808 , G11C29/848 , G11C2029/0409 , G11C2029/0411 , G11C2029/1208
摘要： Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.
摘要翻译：提供了执行ECC操作和冗余修复操作的存储器件和存储器模块。存储器件通过使用纠错码（ECC）操作来修复由于“故障”单元而导致的单位错误，并且当“失败”单元不可修复时，通过使用冗余修复操作来修复“失败”单元通过ECC操作。冗余修复操作包括数据线修复和块修复。 ECC操作可以改变对应于包括“失败”单元的每单位存储器单元的数据的码字，并且还可以改变关于改变的码字的奇偶校验位的大小。

7. 发明授权

US07729195B2 Semiconductor memory device having split word line driver circuit with layout patterns that provide increased integration density 有权
标题翻译：具有分离字线驱动电路的半导体存储器件具有提供增加的集成密度的布局图案
公开(公告)号：US07729195B2
公开(公告)日：2010-06-01
申请号：US11935887
申请日：2007-11-06
申请人： Jae-Youn Youn , Yoon-Hwan Yoon , Sang-Jae Rhee
发明人： Jae-Youn Youn , Yoon-Hwan Yoon , Sang-Jae Rhee
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C5/025 , G11C8/14
摘要： Semiconductor memory devices having hierarchical word line structures are provided. A block of sub-word line driver circuits (SWDB) are disposed between a first block of memory and a second block of memory. A SWDB includes a plurality of sub-wordline driver (SWD) circuits arranged in a plurality of SWD columns each having four SWD circuits extending in a first direction between the first and second blocks of memory. Two adjacent SWD columns include a SWD group for driving a plurality of sub-word lines extending from the SWD group along the first direction into the first and second blocks of memory.
摘要翻译：提供具有分层字线结构的半导体存储器件。一块子字线驱动电路（SWDB）设置在第一存储器块和第二存储器块之间。 SWDB包括布置在多个SWD列中的多个子字线驱动器（SWD）电路，每个SWD列具有在第一和第二存储器块之间沿第一方向延伸的四个SWD电路。两个相邻的SWD列包括用于驱动从SWD组沿着第一方向延伸到第一和第二存储块的多个子字线的SWD组。

8. 发明申请

US20090059682A1 SEMICONDUCTOR MEMORY DEVICE HAVING ANTIFUSE CIRCUITRY 审中-公开
标题翻译：具有抗病毒电路的半导体存储器件
公开(公告)号：US20090059682A1
公开(公告)日：2009-03-05
申请号：US12202902
申请日：2008-09-02
申请人： Bok-Gue Park , Sang-Jae Rhee , Jae-Youn Youn
发明人： Bok-Gue Park , Sang-Jae Rhee , Jae-Youn Youn
IPC分类号： G11C7/00 , G11C29/00 , G11C8/00
CPC分类号： G11C29/02 , G11C29/027 , G11C29/787
摘要： A semiconductor memory device includes a fuse box including a plurality of address antifuse circuits, each address antifuse circuit outputting an address fuse signal according to a program state of an antifuse included in the corresponding address antifuse circuit, an address comparator including a plurality of address comparison signal generators, each address comparison signal generator combining a first test signal for determining an initial defect of the antifuse and a corresponding bit of an externally applied address signal to generate a test address, and comparing the test address with the address fuse signal to generate an address comparison signal, and a redundant enable signal generator for enabling a redundancy enable signal in response to a plurality of address comparison signals.
摘要翻译：一种半导体存储器件，包括一个包括多个地址反熔丝电路的保险丝盒，每个地址反熔丝电路根据相应的地址反熔丝电路中包括的反熔丝的编程状态输出地址熔丝信号，地址比较器包括多个地址比较信号发生器，每个地址比较信号发生器组合用于确定反熔丝的初始缺陷的第一测试信号和外部施加的地址信号的相应位以产生测试地址，以及将测试地址与地址熔丝信号进行比较，以产生地址比较信号，以及冗余使能信号发生器，用于响应于多个地址比较信号启用冗余使能信号。

9. 发明申请

US20070222500A1 Boosting voltage generating circuit for generating a stable boosting voltage under a wider range of supply voltage and semiconductor memory device having the same 有权
标题翻译：用于在更宽的电源电压范围内产生稳定的升压电压的升压电压产生电路和具有该升压电压的半导体存储器件
公开(公告)号：US20070222500A1
公开(公告)日：2007-09-27
申请号：US11707001
申请日：2007-02-16
申请人： Jae Youn Youn , Han Na Park
发明人： Jae Youn Youn , Han Na Park
IPC分类号： G05F1/10
CPC分类号： H02M3/1584 , G11C5/145 , G11C5/147 , G11C8/08
摘要： The boosting voltage generating circuit of example embodiments may include a boosting level detection unit, a first boosting pump, and a second boosting pump. The boosting level detection unit may be configured to generate a target level detection signal and a margin level detection signal. The target level detection signal may have a logic state according to a level of a boosting voltage compared with a target voltage level, and the margin level detection signal may have a logic state according to a level of the boosting voltage compared with a margin voltage level, the margin voltage level being higher than the target voltage level. The first boosting pump may be controlled based on a target voltage level. The second boosting pump may be controlled based on a margin voltage level. According to the boosting voltage generating circuit of example embodiments, overshoot of the boosting voltage by the second boosting pump may remarkably decrease. Accordingly, the boosting voltage generating circuit of example embodiments may generate a stable boosting voltage under a wider range of supply voltage.
摘要翻译：示例性实施例的升压电压产生电路可以包括升压电平检测单元，第一增压泵和第二增压泵。升压电平检测单元可以被配置为产生目标电平检测信号和余量电平检测信号。与目标电压电平相比，目标电平检测信号可以根据升压电压的电平具有逻辑状态，并且边沿电平检测信号可以根据升压电压的电平与余量电压电平相比具有逻辑状态，余量电压电平高于目标电压电平。可以基于目标电压电平来控制第一增压泵。可以基于余量电压电平来控制第二增压泵。根据示例性实施例的升压电压产生电路，第二增压泵的升压电压的过冲可能显着降低。因此，示例性实施例的升压电压产生电路可以在更宽的电源电压范围内产生稳定的升压电压。

10. 发明授权

US07046571B2 Internal voltage generating circuit for periphery, semiconductor memory device having the circuit and method thereof 有权
公开(公告)号：US07046571B2
公开(公告)日：2006-05-16
申请号：US10999353
申请日：2004-11-29
申请人： Jae-Hoon Kim , Jae-Youn Youn
发明人： Jae-Hoon Kim , Jae-Youn Youn
IPC分类号： G11C7/00 , G11C16/04
CPC分类号： G11C5/14 , G11C11/413
摘要： An internal voltage generator for memory bank peripheral circuitry, a semiconductor memory device having the internal voltage generator, and a method for generating an internal voltage are provided. A switchable internal voltage generating circuit according to the present invention includes a control section and an internal voltage generating circuit. The control section generates a control signal in response to a bank activation command and a bank activation signal for enabling memory banks. The internal voltage generating circuit receives a reference voltage, and responds to the control signal to output an internal voltage equal to the reference voltage. The control signal is enabled when the bank activation command and the bank activation signal are concurrently enabled. The bank activation signal is generated in response to a bank address. The internal voltage can be supplied only to peripheral circuits of the banks selected by the bank address, thereby preventing unnecessary power consumption, effectively controlling the internal voltage, and always properly supplying the internal voltage.

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