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21. 发明授权

US5880981A Method and apparatus for reducing the power consumption in a programmable digital signal processor 失效
标题翻译：用于降低可编程数字信号处理器中的功耗的方法和装置
公开(公告)号：US5880981A
公开(公告)日：1999-03-09
申请号：US695617
申请日：1996-08-12
申请人： Hirotsugu Kojima , Avadhani Shridhar
发明人： Hirotsugu Kojima , Avadhani Shridhar
IPC分类号： G06F7/00 , G06F7/544 , G06F9/305 , G06F7/38 , G06F7/52
CPC分类号： G06F7/5443
摘要： The present invention contemplates an improved multiplier circuit and method for reducing power consumption by reducing the number of transitions to the input of the multiplier. Each input to the multiplier is fixed for as long as possible by reordering the sequence of the multiplications to take advantage of duplicate input values. The intermediate results of each multiplication are stored in separate accumulators to obtain the final resultants. Power consumption is further reduced through a reduction in the number of transitions on the data bus linking the multiplier and the data register file containing the accumulators.
摘要翻译：本发明考虑了改进的乘法器电路和方法，用于通过减少向乘法器的输入的转换次数来降低功耗。通过重新排序乘法序列以利用重复输入值，乘法器的每个输入被固定为尽可能长的时间。每个乘法的中间结果存储在单独的累加器中以获得最终的结果。通过减少连接乘法器和包含累加器的数据寄存器文件的数据总线上的转换次数，能够进一步降低功耗。

22. 发明授权

US5519398A Signal processing apparatus having A/D conversion function 失效
标题翻译：具有A / D转换功能的信号处理装置
公开(公告)号：US5519398A
公开(公告)日：1996-05-21
申请号：US135478
申请日：1993-10-13
申请人： Naoki Satoh , Hirotsugu Kojima , Hideki Sawaguchi , Masao Hotta
发明人： Naoki Satoh , Hirotsugu Kojima , Hideki Sawaguchi , Masao Hotta
IPC分类号： G11B5/09 , H03H17/02 , H03H17/06 , H03M1/06 , H03M1/12 , H03M1/14 , H03M1/16 , H03M1/36
CPC分类号： H03M1/0626 , H03M1/148 , H03M1/168 , H03M1/365
摘要： A signal processing apparatus for converting an analog signal to a digital signal and processing the digital signal. In particular, a digital filter for performing processing at high speed is implemented by using an integrated circuit of low power consumption. The signal processing apparatus includes a circuit for comparing an input analog signal with each voltage of a plurality of analog reference voltages and generating a thermometer code Tc depending upon the analog input signal, a decoder for detecting a change point of the thermometer code Tc, and a plurality of memory circuits having output signal lines of the decoder as word selection lines. The product of an input signal value corresponding to each word selection line and a predetermined filter coefficient is stored in the corresponding word of the memory circuits. The memories are used as look-up tables.
摘要翻译：一种用于将模拟信号转换为数字信号并处理数字信号的信号处理装置。特别地，通过使用低功耗的集成电路来实现用于高速执行处理的数字滤波器。该信号处理装置包括用于将输入模拟信号与多个模拟参考电压的每个电压进行比较并根据模拟输入信号产生温度计代码Tc的电路，用于检测温度计代码Tc的变化点的解码器，以及具有解码器的输出信号线作为字选择线的多个存储电路。对应于每个字选择行的输入信号值与预定的滤波器系数的乘积存储在存储器电路的相应字中。这些记忆被用作查找表。

23. 发明授权

US5222035A Digital filter circuit 失效
标题翻译：数字滤波电路
公开(公告)号：US5222035A
公开(公告)日：1993-06-22
申请号：US706389
申请日：1991-05-28
申请人： Junko Nakase , Hirotsugu Kojima
发明人： Junko Nakase , Hirotsugu Kojima
IPC分类号： H03H17/00 , H03H17/02 , H03H17/06
CPC分类号： H03H17/0286 , H03H17/06
摘要： When each sample is expressed by digital signals of 8 bits, 8 bits constituting each of the digital signals are divided into data of upper 5 bits including the most significant bit, and data of lower 4 bits including the least significant bit. These two data are respectively inputted to two filter circuit units, and are simultaneously subjected to a filtering process separately. Outputs of these two filter circuit units are inputted to an adder. In the adder, the output of the filter circuit unit being data of upper 5 bits subjected to a filtering process is weighted by a factor of 2 to the 4th power, and the weighted output is added to the output of the other filter circuit unit. The results of adding are outputted from the adder as signals obtained by the original digital signals of 8 bits subjected to the filtering process. Since the number of bits of individual data is made small by the division, the operation speed of computing elements and the number of times of recursive or multiple uses of computing elements are increased so that the circuit scale of the entire filter circuit can be reduced.
摘要翻译：当每个采样由8位的数字信号表示时，构成每个数字信号的8位被分成包括最高有效位的高5位的数据和包括最低有效位的低4位的数据。这两个数据分别输入到两个滤波电路单元，并分别同时进行滤波处理。这两个滤波器电路单元的输出被输入到加法器。在加法器中，作为经过滤波处理的高5位的数据的滤波器电路单元的输出被加权为2倍至4倍，加权输出相加于另一个滤波电路单元的输出。从作为滤波处理的8位的原始数字信号得到的信号，从加法器输出相加结果。由于通过除法使个别数据的位数变小，所以计算单元的运算速度和运算单元的递归或多次使用次数增加，从而可以减小整个滤波电路的电路规模。

24. 发明授权

US4945506A High speed digital signal processor capable of achieving realtime operation 失效
标题翻译：能实现实时操作的高速数字信号处理器
公开(公告)号：US4945506A
公开(公告)日：1990-07-31
申请号：US324830
申请日：1989-03-17
申请人： Toru Baji , Hirotsugu Kojima , Nario Sumi , Yoshimune Hagiwara , Shinya Ohba
发明人： Toru Baji , Hirotsugu Kojima , Nario Sumi , Yoshimune Hagiwara , Shinya Ohba
IPC分类号： G06F17/10 , G06F17/16
CPC分类号： G06F17/16
摘要： A digital signal processor for computing a vector product between a column vector input signal including a plurality of data items (x0, x1, x2, . . . , x7) and a matrix including a predetermined number of coefficient data items so as to produce a column vector output signal including a plurality of data items (y0, y1, y2, . . . , y7). In a first cycle, the leading data x0 of the column vector input signal is stored in a first store unit (Rin), whereas during this period of time, in a second cycle shorter in time than the first cycle, the data items (c0, c1, c2, . . . , c7) in the row direction constituting a first portion of the matrix are sequentially read out such that both data items are multiplied, thereby storing the multiplication results in an accumulator. A similar data processing is repeatedly executed so as to obtain, based on the outputs from the accumulator, a column vector output signal constituted by the plurality of data items (y0, y1, y2, . . . , y7).
摘要翻译：一种数字信号处理器，用于在包括多个数据项（x0，x1，x2，...，x7）的列向量输入信号和包括预定数量的系数数据项的矩阵之间计算矢量积，以便产生列向量输出信号包括多个数据项（y0，y1，y2，...，y7）。在第一周期中，列向量输入信号的前导数据x0存储在第一存储单元（Rin）中，而在该时间段内，在比第一周期更短的第二周期中，数据项（c0 顺序地读取构成矩阵的第一部分的行方向的c1，c1，c2，...，c7），使得两个数据项被相乘，从而将乘法结果存储在累加器中。重复执行类似的数据处理，以便基于来自累加器的输出，获得由多个数据项（y0，y1，y2，...，y7）构成的列向量输出信号。

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