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21. 发明申请

US20100188121A1 LEAKAGE CURRENT DETECTION CIRCUIT AND LEAKAGE CURRENT COMPARISON CIRCUIT 有权
标题翻译：泄漏电流检测电路和漏电流比较电路
公开(公告)号：US20100188121A1
公开(公告)日：2010-07-29
申请号：US12752389
申请日：2010-04-01
申请人： GUN-OK JUNG
发明人： GUN-OK JUNG
IPC分类号： H03K5/22
CPC分类号： G01R31/275 , G01R31/2621 , G01R31/3008 , H03K2217/0036
摘要： A leakage current measurement circuit measuring a substrate leakage current and a gate leakage current in response to a variation in the size of an MOS transistor and a leakage current comparison circuit judging which one of the substrate leakage current and the gate leakage current is dominant. The leakage current measurement circuit includes a charge supply, a leakage current generator and a detection signal generator. The leakage current comparison circuit includes a charge supply, a leakage current comparator and a detection signal generator.
摘要翻译：泄漏电流测量电路，其响应于MOS晶体管和泄漏电流比较电路的尺寸变化来测量衬底漏电流和栅极漏电流，判断衬底泄漏电流和栅极漏电流中的哪一个占优势。泄漏电流测量电路包括电荷源，漏电流发生器和检测信号发生器。泄漏电流比较电路包括电荷源，漏电流比较器和检测信号发生器。

22. 发明授权

US07623406B2 Accessing semiconductor memory device according to an address and additional access information 失效
标题翻译：根据地址和附加访问信息访问半导体存储器件
公开(公告)号：US07623406B2
公开(公告)日：2009-11-24
申请号：US11705485
申请日：2007-02-12
申请人： Gi-Ho Park , Gun-Ok Jung
发明人： Gi-Ho Park , Gun-Ok Jung
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C11/413 , G11C16/08
摘要： A semiconductor memory device includes a memory cell array, a decoder, and an access control unit. The decoder generates a word line voltage according to an address for a plurality of memory cells in the memory cell array. The access control unit controls access to the plurality of memory cells according to the word line voltage and additional access information separate from the address.
摘要翻译：半导体存储器件包括存储单元阵列，解码器和访问控制单元。解码器根据存储单元阵列中的多个存储单元的地址产生字线电压。访问控制单元根据字线电压和与该地址分离的附加访问信息控制对多个存储器单元的访问。

23. 发明申请

US20100039146A1 High-Speed Multiplexer and Semiconductor Device Including the Same 有权
标题翻译：高速多路复用器和包括其的半导体器件
公开(公告)号：US20100039146A1
公开(公告)日：2010-02-18
申请号：US12540465
申请日：2009-08-13
申请人： Sung Bae Park , Gun Ok Jung , Young Min Shin , Hoi Jin Lee , Chang Jun Choi , Min Su Kim
发明人： Sung Bae Park , Gun Ok Jung , Young Min Shin , Hoi Jin Lee , Chang Jun Choi , Min Su Kim
IPC分类号： H03K3/00
CPC分类号： H03K19/1737 , H03K17/005 , H03K17/693 , H03K19/0013 , H03K2217/0036
摘要： High speed multiplexers include a first N-to-1 selection circuit, where N is an integer greater than one, a second N-to-1 selection circuit and an output driver. The first N-to-1 selection circuit is configured to route a true or complementary version of a selected first input signal (from amongst N input signals) to an output thereof in response to a first multi-bit selection signal, where N is an integer greater than one. The second N-to-1 selection circuit is configured to route a true or complementary version of the selected first input signal to an output thereof in response to a second multi-bit selection signal. The output driver includes a pull-up circuit, which is responsive to a signal generated at the output of the first N-to-1 selection circuit, and a pull-down circuit, which is responsive to a signal generated at the output of the second N-to-1 selection circuit.
摘要翻译：高速多路复用器包括第一N-1选择电路，其中N是大于1的整数，第二N-1选择电路和输出驱动器。第一N-1选择电路被配置为响应于第一多位选择信号将所选择的第一输入信号（从N个输入信号中）的真或互补版本路由到其输出，其中N是大于1的整数。第二N-1选择电路被配置为响应于第二多位选择信号将所选择的第一输入信号的真实或互补版本路由到其输出。输出驱动器包括上拉电路，其响应于在第一N-1选择电路的输出处产生的信号，以及下拉电路，其响应于在输出端产生的信号第二个N到1选择电路。

24. 发明授权

US07595665B2 Clock gated circuit 失效
标题翻译：时钟门控电路
公开(公告)号：US07595665B2
公开(公告)日：2009-09-29
申请号：US12009903
申请日：2008-01-23
申请人： Jin-soo Park , Gun-ok Jung
发明人： Jin-soo Park , Gun-ok Jung
IPC分类号： H03K19/096
CPC分类号： H03K19/0016
摘要： A clock gated circuit includes a clock signal receiving unit that applies a first voltage to a fighting node when the clock signal is at a first logic; a discharging unit that discharges an electric charge from the fighting node when the clock signal is transitioned from the first logic to a second logic and when the enable signal is activated; a voltage maintaining unit that maintains the fighting node at a power or ground voltage; and an output unit that inverts a logic level of the fighting node to generate the gated clock signal. A blocking unit can be included that blocks a power voltage from being provided to the fighting node by the voltage maintaining unit when discharging. A blocking transistor can be included that prevents unnecessary electric charge from inflowing into the fighting node to reduce power consumption and discharging time.
摘要翻译：时钟门控电路包括时钟信号接收单元，当时钟信号处于第一逻辑时，该时钟信号接收单元将第一电压施加到战斗节点; 放电单元，当时钟信号从第一逻辑转换到第二逻辑时以及当使能信号被激活时，从战斗节点排出电荷; 保持所述战斗节点处于电力或接地电压的电压保持单元; 以及输出单元，其反转战斗节点的逻辑电平以产生门控时钟信号。可以包括阻塞单元，其阻止在放电时由电压保持单元提供给战斗节点的电源电压。可以包括阻止不必要的电荷流入战斗节点以减少功耗和放电时间的阻塞晶体管。

25. 发明申请

US20080204081A1 Clock gated circuit 失效
标题翻译：时钟门控电路
公开(公告)号：US20080204081A1
公开(公告)日：2008-08-28
申请号：US12009903
申请日：2008-01-23
申请人： Jin-soo Park , Gun-ok Jung
发明人： Jin-soo Park , Gun-ok Jung
IPC分类号： H03K19/096
CPC分类号： H03K19/0016
摘要： A clock gated circuit includes a clock signal receiving unit that applies a first voltage to a fighting node when the clock signal is at a first logic; a discharging unit that discharges an electric charge from the fighting node when the clock signal is transitioned from the first logic to a second logic and when the enable signal is activated; a voltage maintaining unit that maintains the fighting node at a power or ground voltage; and an output unit that inverts a logic level of the fighting node to generate the gated clock signal. A blocking unit can be included that blocks a power voltage from being provided to the fighting node by the voltage maintaining unit when discharging. A blocking transistor can be included that prevents unnecessary electric charge from inflowing into the fighting node to reduce power consumption and discharging time.
摘要翻译：时钟门控电路包括时钟信号接收单元，当时钟信号处于第一逻辑时，该时钟信号接收单元将第一电压施加到战斗节点; 放电单元，当时钟信号从第一逻辑转换到第二逻辑时以及当使能信号被激活时，从战斗节点排出电荷; 保持所述战斗节点处于电力或接地电压的电压保持单元; 以及输出单元，其反转战斗节点的逻辑电平以产生门控时钟信号。可以包括阻塞单元，其阻止在放电时由电压保持单元提供给战斗节点的电源电压。可以包括阻止不必要的电荷流入战斗节点以减少功耗和放电时间的阻塞晶体管。

26. 发明授权

US07348837B2 Point diffusion signal distribution with minimized power consumption and signal skew 有权
标题翻译：点扩散信号分布，功耗和信号偏移最小化
公开(公告)号：US07348837B2
公开(公告)日：2008-03-25
申请号：US11297004
申请日：2005-12-08
申请人： Gun-Ok Jung , Young-Min Shin
发明人： Gun-Ok Jung , Young-Min Shin
IPC分类号： H01L25/00
CPC分类号： G06F1/10
摘要： For distributing a signal to loads in an area, the area is divided into a plurality of regions. A respective signal point is disposed in each region for providing the signal to a load in the region. A respective diffusion point is disposed between any two neighboring signal points. The signal is initially applied to a center point of the signal and diffusion points. The signal when received at a given signal or diffusion point is transmitted to any of the signal or diffusion points within a maximum distance from the given signal or diffusion point.
摘要翻译：为了将信号分配到区域中的负载，该区域被分成多个区域。相应的信号点设置在每个区域中，用于向该区域中的负载提供信号。相应的扩散点设置在任何两个相邻信号点之间。信号最初被施加到信号和扩散点的中心点。在给定信号或扩散点处接收到的信号被传送到与给定信号或扩散点的最大距离内的任何信号或扩散点。

27. 发明申请

US20050052211A1 Delayed clock signal generator 有权
标题翻译：延时时钟信号发生器
公开(公告)号：US20050052211A1
公开(公告)日：2005-03-10
申请号：US10910644
申请日：2004-08-04
申请人： Gun-Ok Jung , Jin-Han Kim , Sung-Bae Park , Chul-Woo Kim , Seok-Soo Yoon , Seok-Ryoung Yoon
发明人： Gun-Ok Jung , Jin-Han Kim , Sung-Bae Park , Chul-Woo Kim , Seok-Soo Yoon , Seok-Ryoung Yoon
IPC分类号： G06F1/06 , H03H11/26 , H03K5/00 , H03K5/05 , H03K5/13 , H03K5/135 , H03K5/15 , H03K5/26 , H03L7/081 , H04L7/02
CPC分类号： H03K5/133 , H03K5/135 , H03K2005/00156 , H03K2005/00286
摘要： A device which may be configured to generate delayed clock signals by a specified phase difference, which may include a clock generator circuit for generating at least one clock signal, a delayed clock signal generator for delaying the at least one clock signal, a phase detect circuit for generating a selecting signal based on the amount of phase delay detected according to a half-cycle (π), and in comparison with the clock signal, a phase interpolation circuit for controlling the delay time of the delayed clock signals and interpolating the delayed clock signals, and a selecting circuit which outputs the delayed clock signal delayed by a specified phase difference.
摘要翻译：一种可以被配置为通过指定的相位差产生延迟的时钟信号的装置，其可以包括用于产生至少一个时钟信号的时钟发生器电路，用于延迟所述至少一个时钟信号的延迟时钟信号发生器，相位检测电路用于基于根据半周期（pi）检测到的相位延迟量来生成选择信号，并且与时钟信号相比，相位插值电路用于控制延迟的时钟信号的延迟时间并内插延迟的时钟信号，以及输出延迟了指定相位差的延迟时钟信号的选择电路。

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