专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06868474B2 High performance cost optimized memory 失效
公开(公告)号：US06868474B2
公开(公告)日：2005-03-15
申请号：US10128167
申请日：2002-04-22
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G11C7/10 , G11C7/12 , G11C11/4096 , G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.

22. 发明授权

US06788593B2 Asynchronous, high-bandwidth memory component using calibrated timing elements 失效
标题翻译：异步高带宽内存组件使用校准的时序元素
公开(公告)号：US06788593B2
公开(公告)日：2004-09-07
申请号：US09796924
申请日：2001-02-28
申请人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
发明人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C700
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1039 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.
摘要翻译：这里公开了使用内部延迟元件来启用存储器访问流水线的异步存储器件的实施例。在一个实施例中，延迟元件响应于输入负载控制信号，并且参考周期性接收的定时脉冲进行校准。不同数量的延迟元件被配置为产生不同的异步延迟并选择存储器件的顺序流水线元件。

23. 发明授权

US06553452B2 Synchronous memory device having a temperature register 有权
标题翻译：具有温度寄存器的同步存储器件
公开(公告)号：US06553452B2
公开(公告)日：2003-04-22
申请号：US10051957
申请日：2002-01-18
申请人： Bruno Werner Garlepp , Pak Shing Chau , Kevin S. Donnelly , Clemenz Portmann , Donald C. Stark , Stefanos Sidiropoulos , Richard M. Barth , Paul G. Davis , Ely K. Tsern
发明人： Bruno Werner Garlepp , Pak Shing Chau , Kevin S. Donnelly , Clemenz Portmann , Donald C. Stark , Stefanos Sidiropoulos , Richard M. Barth , Paul G. Davis , Ely K. Tsern
IPC分类号： G06F1200
CPC分类号： G11C7/1048 , G06F13/1689 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： A synchronous dynamic random access memory device having an array of dynamic memory cells. The memory device includes input receiver circuitry to sample a value that is representative of a range of temperatures. In addition, the memory device includes a programmable register, coupled to the input receiver circuitry, to store the value that is representative of the range of temperatures.
摘要翻译：一种具有动态存储单元阵列的同步动态随机存取存储器件。存储器件包括用于对表示温度范围的值进行采样的输入接收器电路。此外，存储器件包括耦合到输入接收器电路的可编程寄存器，以存储代表温度范围的值。

24. 发明授权

US06401167B1 High performance cost optimized memory 失效
公开(公告)号：US06401167B1
公开(公告)日：2002-06-04
申请号：US09169206
申请日：1998-10-09
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G06F1200
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.

25. 发明授权

US06378018B1 Memory device and system including a low power interface 有权
标题翻译：存储器件和系统包括低功率接口
公开(公告)号：US06378018B1
公开(公告)日：2002-04-23
申请号：US09169506
申请日：1998-10-09
申请人： Ely K. Tsern , Thomas J. Holman , Richard M. Barth , Andrew V. Anderson , Paul G. Davis , Craig E. Hampel , Donald C. Stark , Abhijit M. Abhyankar
发明人： Ely K. Tsern , Thomas J. Holman , Richard M. Barth , Andrew V. Anderson , Paul G. Davis , Craig E. Hampel , Donald C. Stark , Abhijit M. Abhyankar
IPC分类号： G06F1300
CPC分类号： G06F13/4243 , G06F13/1694 , Y02D10/14 , Y02D10/151
摘要： A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power interface for coupling to the low speed channel. The memory device is operative in a low power mode and a high power mode. A memory controller is coupled to the high speed channel and the low speed channel of the interconnect structure. The memory controller is configured to transmit control information over the low speed channel to set the power mode of the memory device. The memory device is operative in a low power mode during which high power receiver circuits are turned off. The memory device is also operative in a nap mode during which an internal clock compensation circuit is left on to preserve phase information. The memory system may include multiple memory devices coupled to a daisy chained lead of the interconnect structure. The memory controller may be configured to apply control information to the interconnect structure as an encoded device identification word. The memory devices may each include a decoder for interpreting the encoded device identification word. The memory controller may be configured to apply a memory device selection signal to the interconnect structure to selectively enable the memory devices.
摘要翻译：存储器系统包括具有高速通道和低速通道的互连结构。具有接口电路的存储器件耦合到互连结构。接口电路包括用于耦合到高速通道的高功率接口和用于耦合到低速通道的低功率接口。存储器件在低功率模式和高功率模式下工作。存储器控制器耦合到互连结构的高速通道和低速通道。存储器控制器被配置为通过低速信道发送控制信息以设置存储器件的功率模式。存储器件在低功率模式下工作，在此期间高功率接收器电路被关闭。存储器装置还可以在休眠模式下工作，在此模式期间内部时钟补偿电路被保留以保持相位信息。存储器系统可以包括耦合到互连结构的菊花链引导件的多个存储器件。存储器控制器可以被配置为将控制信息作为编码设备标识字应用于互连结构。存储器件可以各自包括用于解释编码器件识别字的解码器。存储器控制器可以被配置为将存储器件选择信号施加到互连结构以选择性地启用存储器件。

26. 再颁专利

USRE37409E1 Memory and method for sensing sub-groups of memory elements 有权
标题翻译：用于感测存储器元件子组的存储器和方法
公开(公告)号：USRE37409E1
公开(公告)日：2001-10-16
申请号：US09559836
申请日：2000-04-26
申请人： Richard M. Barth , Donald C. Stark , Lawrence Lai , Wayne S. Richardson
发明人： Richard M. Barth , Donald C. Stark , Lawrence Lai , Wayne S. Richardson
IPC分类号： G11C1300
CPC分类号： G11C7/06 , G11C8/14 , G11C11/4085 , G11C11/4091
摘要： A memory and method of operation is disclosed. In one embodiment, the memory includes a group of memory cells divided into a plurality of subgroups. Sub word-lines are selectively coupled to main word lines, each sub-word line corresponding to a subgroup and is coupled to the memory cells in the row of the corresponding subgroup. Sense amplifier circuitry is coupled to the group of memory cells. The sense amplifier circuitry is divided into a plurality of sub-sensing circuits, each of the plurality of sub-sensing circuits selectively coupled to a corresponding one of the plurality of sub-groups. The memory includes a control mechanism to control the word lines and sub-sensing circuit (s) that are activated at any one time such that only those sub-word lines and sub-sensing circuits needed to perform memory operations are operated and consume power. In an alternate embodiment, the control mechanism controls the sub-word lines and sub-sensing circuits to enable substantially concurrent access to different sub-groups of memory cells from different rows of the memory.
摘要翻译：公开了一种存储器和操作方法。在一个实施例中，存储器包括分成多个子组的一组存储器单元。子字线选择性地耦合到主字线，每个子字线对应于一个子组，并且被耦合到相应子组的行中的存储器单元。感测放大器电路耦合到该组存储器单元。感测放大器电路被分成多个子感测电路，多个子感测电路中的每一个选择性地耦合到多个子组中对应的一个子组。存储器包括一个控制机构，用于控制在任何一个时间被激活的字线和子感应电路，使得只需要执行存储器操作所需的子字线和子感测电路并消耗功率。在替代实施例中，控制机构控制子字线和子感测电路以使得能够从存储器的不同行实质上并发地访问存储器单元的不同子组。

27. 发明授权

US06134172A Apparatus for sharing sense amplifiers between memory banks 失效
标题翻译：用于在存储体之间共享读出放大器的装置
公开(公告)号：US06134172A
公开(公告)日：2000-10-17
申请号：US862641
申请日：1997-05-23
申请人： Richard M. Barth , Donald C. Stark , Ely K. Tsern
发明人： Richard M. Barth , Donald C. Stark , Ely K. Tsern
IPC分类号： G11C7/00 , G11C7/06 , G11C11/409 , G11C8/00
CPC分类号： G11C7/00 , G11C11/409 , G11C7/06
摘要： A memory device includes a first memory bank and a second memory bank, each memory bank having at least one subarray of memory cells. Multiple sense amplifiers are coupled to at least one subarray of memory cells. At least one sense amplifier is configured for use by both the first memory bank and the second memory bank, but not simultaneously. The sharing of sense amplifiers between memory banks minimizes the die area penalty caused by additional memory banks. The memory device is configured such that the first memory bank is adjacent to the second memory bank.
摘要翻译：存储器件包括第一存储体和第二存储体，每个存储体具有至少一个存储单元的子阵列。多个读出放大器耦合到存储器单元的至少一个子阵列。至少一个读出放大器被配置为由第一存储体和第二存储体使用，但不能同时使用。存储器组之间的读出放大器的共享使由附加存储体引起的管芯面积损失最小化。存储器件被配置为使得第一存储体与第二存储体相邻。

28. 发明授权

US5825209A Quadrature phase detector 失效
标题翻译：正交相位检测器
公开(公告)号：US5825209A
公开(公告)日：1998-10-20
申请号：US807642
申请日：1997-02-27
申请人： Donald C. Stark , Wayne S. Richardson
发明人： Donald C. Stark , Wayne S. Richardson
IPC分类号： H03L7/085 , H03K5/26
CPC分类号： H03L7/085
摘要： A quadrature phase detector includes a first load and a current source circuit. A first differential circuit and a second differential circuit coupled to the first load. In response to a first input signal, a first switching circuit couples the current source to the first differential circuit to form a first differential amplifier. The first switching circuit also couples the current source to the second differential circuit to form a second differential amplifier. The second differential amplifier is cross-coupled to the first differential amplifier. The first and second differential amplifiers are coupled to receive a differential second input signal, wherein the first and second input signals have a substantially different signal swing. A second switching circuit couples the current source to a second load in response to the complement of the first input signal. The cross-coupled first and second differential amplifiers provide a differential output signal corresponding to a quadrature phase error between the first and differential second input signals.
摘要翻译：正交相位检测器包括第一负载和电流源电路。耦合到第一负载的第一差分电路和第二差分电路。响应于第一输入信号，第一开关电路将电流源耦合到第一差分电路以形成第一差分放大器。第一开关电路还将电流源耦合到第二差分电路以形成第二差分放大器。第二差分放大器交叉耦合到第一差分放大器。第一和第二差分放大器耦合以接收差分第二输入信号，其中第一和第二输入信号具有基本上不同的信号摆幅。第二开关电路响应于第一输入信号的补码将电流源耦合到第二负载。交叉耦合的第一和第二差分放大器提供对应于第一和第二输入信号之间的正交相位误差的差分输出信号。

29. 发明授权

US08313712B2 Microfluidic valve with pressure gain 失效
标题翻译：带有压力增益的微流控阀
公开(公告)号：US08313712B2
公开(公告)日：2012-11-20
申请号：US12660797
申请日：2010-03-03
申请人： Jessica E. Melin , Donald C. Stark , James A. Weaver
发明人： Jessica E. Melin , Donald C. Stark , James A. Weaver
IPC分类号： B01L99/00
CPC分类号： F16K99/0059 , B01L3/502707 , B01L3/502738 , B01L2300/0816 , B01L2300/0887 , B01L2300/14 , B01L2400/0638 , F16K99/0001 , F16K2099/008 , Y10T137/7761
摘要： The current invention provide a microfluidic valve having a housing that includes a microfluid control port disposed adjacent to a microfluid exhaust port, where a movable rigid material having a first diameter is disposed in the housing between the microfluid control port and the microfluid exhaust port. The housing further includes a microfluid pressure port having a first microfluid pressure. The microfluid pressure port is connected to the microfluid exhaust port by a microfluid valve orifice having a second diameter, where the first diameter is larger than the second diameter, and when a second microfluid pressure is applied to the control port the moveable rigid material closes the microfluid valve orifice, where the first microfluid pressure is greater than the second microfluid pressure.
摘要翻译：本发明提供了一种微流体阀，其具有壳体，该壳体包括邻近微流体排出口设置的微流体控制端口，其中具有第一直径的可移动刚性材料设置在微流体控制端口和微流体排出口之间的壳体中。壳体还包括具有第一微流体压力的微流体压力端口。微流体压力端口通过具有第二直径的微流体阀孔连接到微流体排出口，第一直径大于第二直径，当向控制端口施加第二微流体压力时，可动刚性材料将微流体阀孔，其中第一微流体压力大于第二微流体压力。

30. 发明申请

US20120134084A1 Memory Modules and Devices Supporting Configurable Core Organizations 有权
标题翻译：支持可配置核心组织的内存模块和设备
公开(公告)号：US20120134084A1
公开(公告)日：2012-05-31
申请号：US13365890
申请日：2012-02-03
申请人： Richard E. Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
发明人： Richard E. Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： H05K7/00
CPC分类号： G06F13/1678 , G06F12/04 , G06F12/06 , G06F12/0646 , G06F13/1657 , G06F13/4022 , G11C5/02 , G11C5/025 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C7/1045 , G11C7/1048 , G11C7/106 , G11C7/1072 , G11C7/1087 , G11C8/06 , G11C11/4087 , G11C11/4097 , G11C2207/105 , G11C2207/108 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14
摘要： Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.
摘要翻译：描述了组织在存储器子部分中并且包括可配置路由以支持多个数据宽度配置的存储器设备。相对窄的宽度配置加载较少的读出放大器，导致相对较窄的存储器配置的功率消耗减少。还描述了将宽度选择信息传送到可配置的存储装置并支持多个宽度配置的点对点数据接口的存储器控制器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式