专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20080030249A1 Measure control delay and method having latching circuit integral with delay circuit 有权
公开(公告)号：US20080030249A1
公开(公告)日：2008-02-07
申请号：US11900451
申请日：2007-09-11
申请人： David Zimlich
发明人： David Zimlich
IPC分类号： H03H11/26
CPC分类号： G11C7/22 , G11C7/222 , G11C11/4076 , H03K5/135
摘要： A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A digital signal is applied to an initial delay unit in the measuring delay line and it sequentially propagates through the delay units until a second digital signal is received. These outputs are applied to control inputs to the signal generating delay line to control the number of delay units through which a clock signal propagates before being output from a final delay unit. Each of the delay units in the measuring delay line includes a pair of series connected NOR gates. A NOR gate to which the digital signal is initially applied is coupled to a second NOR gate as a flip-flop so that the output of the NOR gate remains constant after the digital signal has been applied to the measuring delay line.

22. 发明申请

US20070159237A1 Semiconductor temperature sensor using bandgap generator circuit 有权
标题翻译：半导体温度传感器采用带隙发生器电路
公开(公告)号：US20070159237A1
公开(公告)日：2007-07-12
申请号：US11330987
申请日：2006-01-12
申请人： David Zimlich
发明人： David Zimlich
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A combined bandgap generator and temperature sensor for an integrated circuit is disclosed. Embodiments of the invention recognize that bandgap generators typically contain at least one temperature-sensitive element for the purpose of cancelling temperature sensitivity out of the reference voltage the bandgap generator produces. Accordingly, this same temperature-sensitive element is used in accordance with the invention as the means for indicating the temperature of the integrated circuit, without the need to fabricate a temperature sensor separate and apart from the bandgap generator. Specifically, in one embodiment, a voltage across a temperature-sensitive junction from a bandgap generator is assessed in a temperature conversion stage portion of the combined bandgap generator and temperature sensor circuit. Assessment of this voltage can be used to produce a voltage- or current-based output indicative of the temperature of the integrated circuit, which output can be binary or analog in nature.
摘要翻译：公开了一种用于集成电路的组合带隙发生器和温度传感器。本发明的实施例认识到，带隙发生器通常包含至少一个温度敏感元件，以便在带隙发生器产生的参考电压之外消除温度敏感性。因此，根据本发明使用相同的温度敏感元件作为用于指示集成电路的温度的装置，而不需要制造分离和分离带隙发生器的温度传感器。具体地，在一个实施例中，在组合带隙发生器和温度传感器电路的温度转换级部分中评估来自带隙发生器的温度敏感结两端的电压。可以使用该电压的评估来产生指示集成电路的温度的基于电压或电流的输出，该输出本质上可以是二进制或模拟的。

23. 发明申请

US20060203606A1 System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal 有权
公开(公告)号：US20060203606A1
公开(公告)日：2006-09-14
申请号：US11433216
申请日：2006-05-11
申请人： David Zimlich
发明人： David Zimlich
IPC分类号： G11C8/00
CPC分类号： G11C7/222 , G11C7/22 , G11C11/4076 , H03H11/26
摘要： Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock signal. A second series of feedback delay circuits mirror respective first delay circuits. After the input signal has been coupled through the first delay circuits, the mirrored signals from the first delay circuits are coupled through the feedback delay circuits. The delay of the feedback delay circuits is one-half the delay of the first delay circuits to provide a signal that is the quadrature of the clock signal.

24. 发明申请

US20060202729A1 System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal 有权
标题翻译：具有相对于输入时钟信号选择相位的输出时钟信号的降低功率开环合成的系统和方法
公开(公告)号：US20060202729A1
公开(公告)日：2006-09-14
申请号：US11430471
申请日：2006-05-08
申请人： Tyler Gomm , David Zimlich
发明人： Tyler Gomm , David Zimlich
IPC分类号： H03K5/13
CPC分类号： H03K5/00006 , G11C7/1027 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C11/406 , G11C11/4076 , G11C11/408 , G11C11/4093 , H03K5/135 , H03K2005/00286
摘要： A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled to a series of latches that correspond to respective groups of delay elements in the measurement delay line. The delay element to which the pulse has propagated when the next pulse is received causes a corresponding latch to be set. The clock reference signal propagates through a signal generating delay line, which contains a sub-multiple of the number of delay elements in the measurement delay line, starting at a location corresponding to the set latch. The latch may remain set for a large number of periods of the clock reference signal so that it is not necessary for the clock reference signal to propagate through the measurement delay line each cycle.
摘要翻译：信号发生电路包括产生响应于周期性时钟参考信号的脉冲的脉冲发生器。脉冲通过测量延迟线中的多个串联延迟元件传播。测量延迟线耦合到对应于测量延迟线中的相应延迟元件组的一系列锁存器。当接收下一个脉冲时脉冲已经传播的延迟元件使得相应的锁存器被置位。时钟参考信号通过信号产生延迟线传播，该信号产生延迟线包含测量延迟线中的延迟元件数量的子倍数，从对应于设置的锁存器的位置开始。锁存器可以保持设置时钟参考信号的大量周期，使得时钟参考信号不必每个周期通过测量延迟线传播。

25. 发明授权

US07078951B2 System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal 失效
公开(公告)号：US07078951B2
公开(公告)日：2006-07-18
申请号：US10928424
申请日：2004-08-27
申请人： Tyler Gomm , David Zimlich
发明人： Tyler Gomm , David Zimlich
IPC分类号： H03H11/26
CPC分类号： H03K5/00006 , G11C7/1027 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C11/406 , G11C11/4076 , G11C11/408 , G11C11/4093 , H03K5/135 , H03K2005/00286
摘要： A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled to a series of latches that correspond to respective groups of delay elements in the measurement delay line. The delay element to which the pulse has propagated when the next pulse is received causes a corresponding latch to be set. The clock reference signal propagates through a signal generating delay line, which contains a sub-multiple of the number of delay elements in the measurement delay line, starting at a location corresponding to the set latch. The latch may remain set for a large number of periods of the clock reference signal so that it is not necessary for the clock reference signal to propagate through the measurement delay line each cycle.

26. 发明申请

US20060044037A1 System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal 失效
公开(公告)号：US20060044037A1
公开(公告)日：2006-03-02
申请号：US10928424
申请日：2004-08-27
申请人： Tyler Gomm , David Zimlich
发明人： Tyler Gomm , David Zimlich
IPC分类号： H03H11/26
CPC分类号： H03K5/00006 , G11C7/1027 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C11/406 , G11C11/4076 , G11C11/408 , G11C11/4093 , H03K5/135 , H03K2005/00286
摘要： A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled to a series of latches that correspond to respective groups of delay elements in the measurement delay line. The delay element to which the pulse has propagated when the next pulse is received causes a corresponding latch to be set. The clock reference signal propagates through a signal generating delay line, which contains a sub-multiple of the number of delay elements in the measurement delay line, starting at a location corresponding to the set latch. The latch may remain set for a large number of periods of the clock reference signal so that it is not necessary for the clock reference signal to propagate through the measurement delay line each cycle.

27. 发明授权

US06509578B1 Method and structure for limiting emission current in field emission devices 失效
公开(公告)号：US06509578B1
公开(公告)日：2003-01-21
申请号：US09679834
申请日：2000-10-05
申请人： David Zimlich
发明人： David Zimlich
IPC分类号： H01L21266
CPC分类号： H01J9/025 , H01J1/3042
摘要： A field emission display has electron emitters that are current-limited by implanting in a silicon layer only enough ions to produce a desired current, and then forming emitters from the silicon layer by isotropic etching.

28. 发明授权

US06130106A Method for limiting emission current in field emission devices 失效
标题翻译：用于限制场致发射器件中的发射电流的方法
公开(公告)号：US06130106A
公开(公告)日：2000-10-10
申请号：US748816
申请日：1996-11-14
申请人： David Zimlich
发明人： David Zimlich
IPC分类号： H01J1/304 , H01J9/02 , H01L21/266
CPC分类号： H01J9/025 , H01J1/3042
摘要： A field emission display has electron emitters that are current-limited by implanting in a silicon layer only enough ions to produce a desired current, and then forming emitters from the silicon layer by isotropic etching.
摘要翻译：场发射显示器具有通过仅在足够的离子产生所需电流的硅层中注入电流限制的电子发射体，然后通过各向同性蚀刻从硅层形成发射体。

29. 发明授权

US5857884A Photolithographic technique of emitter tip exposure in FEDS 失效
标题翻译： FEDS中发射极尖端曝光的光刻技术
公开(公告)号：US5857884A
公开(公告)日：1999-01-12
申请号：US598236
申请日：1996-02-07
申请人： David Zimlich
发明人： David Zimlich
IPC分类号： H01J9/02
CPC分类号： H01J9/025
摘要： Aligned gate structures for field emitter display devices are formed by overlaying a substrate, having at least one emitter tip thereon, successively with an insulating layer, a conductive layer, and a photoresist layer. The photoresist layer is then exposed to create fixed and unfixed regions. The unfixed regions are developed and etched to remove the conductive layer under the unfixed regions. The insulating layer is then etched to expose the emitter tips and the photoresist layer removed.
摘要翻译：用于场致发射器显示器件的对准栅极结构通过在绝缘层，导电层和光致抗蚀剂层上依次覆盖其上具有至少一个发射极尖端的衬底而形成。然后曝光光致抗蚀剂层以产生固定和未固定的区域。未固定区域被显影和蚀刻以除去未固定区域下的导电层。然后蚀刻绝缘层以暴露发射极尖端并去除光致抗蚀剂层。

30. 发明授权

US08811920B2 DC-DC converter semiconductor die structure 有权
标题翻译： DC-DC转换器半导体管芯结构
公开(公告)号：US08811920B2
公开(公告)日：2014-08-19
申请号：US13287713
申请日：2011-11-02
申请人： Robert Deuchars , Jean-Christophe Berchtold , Joseph Hubert Colles , David Zimlich , Chris Levesque , William David Southcombe , David E. Jones , Scott Yoder , Terry J. Stockert
发明人： Robert Deuchars , Jean-Christophe Berchtold , Joseph Hubert Colles , David Zimlich , Chris Levesque , William David Southcombe , David E. Jones , Scott Yoder , Terry J. Stockert
IPC分类号： H01Q11/12 , H04B1/28
CPC分类号： H03F1/0227 , H03F1/0261 , H03F1/0277 , H03F3/195 , H03F3/211 , H03F3/245 , H03F3/602 , H03F3/72 , H03F2200/171 , H03F2200/222 , H03F2200/27 , H03F2200/318 , H03F2200/336 , H03F2200/387 , H03F2200/411 , H03F2200/414 , H03F2200/417 , H03F2200/451 , H03F2200/504 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2203/21106 , H03F2203/21142 , H03F2203/21157
摘要： A direct current (DC)-DC converter having a DC-DC converter semiconductor die and an alpha flying capacitive element is disclosed. The DC-DC converter semiconductor die includes a first series alpha switching element, a second series alpha switching element, a first alpha flying capacitor connection node, which is about over the second series alpha switching element, and a second alpha flying capacitor connection node, which is about over the first series alpha switching element. The alpha flying capacitive element is electrically coupled between the first alpha flying capacitor connection node and the second alpha flying capacitor connection node. By locating the first alpha flying capacitor connection node and the second alpha flying capacitor connection node about over the second series alpha switching element and the first series alpha switching element, respectively, lengths of transient current paths may be minimized, thereby reducing noise and potential interference.
摘要翻译：公开了具有DC-DC转换器半导体管芯和α型飞行电容元件的直流（DC）-DC转换器。 DC-DC转换器半导体管芯包括第一系列α开关元件，第二串联α开关元件，大约在第二串联α开关元件上方的第一α型飞秒电容器连接节点和第二α型飞秒电容器连接节点，这是关于超过第一系列α开关元件。 α飞行电容元件电耦合在第一α型飞秒电容器连接节点和第二α型飞秒电容器连接节点之间。通过分别在第二系列α开关元件和第一系列α开关元件周围定位第一个α飞秒电容器连接节点和第二个α飞秒电容器连接节点，可以将瞬态电流路径的长度最小化，从而降低噪声和潜在干扰。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式