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21. 发明授权

US07656327B2 Saturation detection for analog-to-digital converter 失效
标题翻译：模数转换器的饱和度检测
公开(公告)号：US07656327B2
公开(公告)日：2010-02-02
申请号：US11564546
申请日：2006-11-29
申请人： Daniel F. Filipovic , Christos Komninakis
发明人： Daniel F. Filipovic , Christos Komninakis
IPC分类号： H03M1/62
CPC分类号： H03M1/183 , H03G3/3052 , H04L25/061 , H04L25/063
摘要： This disclosure describes techniques for detecting or predicting saturation of an analog-to-digital converter. The techniques analyze digital samples following analog-to-digital conversion, and count occurrences of specific values associated with a subset of bits within the digital samples. The specific subset of bits that are used detect or predict saturation may vary depending on the analog-to-digital converter and the number of bits in the digital samples. However, the techniques avoid the need to consider every bit in the digital samples, and rely only on a subset of bits (one or more), which can simplify the counting algorithms used in the saturation detection or prediction. Upon identifying a probable saturation state of the analog-to-digital converter based on the counting, the techniques may de-boost the gain of an analog amplifier. This can effectively extend the dynamic range of the analog-to-digital converter.
摘要翻译：本公开描述了用于检测或预测模数转换器的饱和度的技术。该技术分析模数转换后的数字样本，并计数与数字样本中的位子集相关联的特定值的出现。用于检测或预测饱和的位的特定子集可以根据模数转换器和数字样本中的位数而变化。然而，这些技术避免了考虑数字采样中的每一位，并且仅依赖于一个位（一个或多个）的子集，这可以简化在饱和检测或预测中使用的计数算法。在基于计数识别模数转换器的可能的饱和状态时，这些技术可以降低模拟放大器的增益。这可以有效地扩展模数转换器的动态范围。

22. 发明申请

US20090279591A1 FREQUENCY SPUR DETECTION AND SUPPRESSION 有权
标题翻译：频率检测和抑制
公开(公告)号：US20090279591A1
公开(公告)日：2009-11-12
申请号：US12116539
申请日：2008-05-07
申请人： Daniel Fred Filipovic , Helena Deirdre O'Shea , Christos Komninakis , Jifeng Geng
发明人： Daniel Fred Filipovic , Helena Deirdre O'Shea , Christos Komninakis , Jifeng Geng
IPC分类号： H04B1/10 , H04B1/707 , H04J13/04
CPC分类号： H04B1/1036 , H04B1/7107
摘要： Techniques for identifying and suppressing frequency spurs in a signal are disclosed. In an embodiment, an incoming signal is rotated by a frequency related to a spur frequency, and an estimate of the content of the rotated signal is derived. The estimate may be subtracted from the rotated incoming signal, and the result de-rotated by the spur frequency. In an embodiment, the incoming signal may be rotated such that the spur is centered at DC. In an alternative embodiment, the estimate may be de-rotated before being subtracted from the original incoming signal. Techniques for addressing multiple spurs using serial and parallel architectures are disclosed. Further disclosed are techniques for searching for the presence of spurs in an incoming signal, and tracking spur frequencies over time.
摘要翻译：公开了用于识别和抑制信号中的频率杂散的技术。在一个实施例中，输入信号被旋转与杂波频率相关的频率，并且导出旋转信号的内容的估计。可以从旋转的输入信号中减去估计值，并且结果由杂散频率去旋转。在一个实施例中，输入信号可以旋转，使得支线以DC为中心。在替代实施例中，估计可以在从原始输入信号中减去之前被去转动。公开了使用串行和并行架构寻址多个杂散的技术。进一步公开的是用于在输入信号中搜索马刺的存在以及随时间跟踪刺激频率的技术。

23. 发明申请

US20090164827A1 METHOD AND APPARATUS FOR GENERATING OR UTILIZING ONE OR MORE CYCLE-SWALLOWED CLOCK SIGNALS 有权
标题翻译：用于产生或利用一个或多个循环时钟信号的方法和装置
公开(公告)号：US20090164827A1
公开(公告)日：2009-06-25
申请号：US12053433
申请日：2008-03-21
申请人： Christos Komninakis , Ming-Chieh Kuo
发明人： Christos Komninakis , Ming-Chieh Kuo
IPC分类号： G06F1/00
CPC分类号： H03L7/00
摘要： An electronic device is provided for generating or utilizing one or more cycle-swallowed clock signals derived based on one or more first clock signals. The device includes a module configured to receive a first clock signal having a first frequency. The module is configured to generate a second clock signal having a second frequency and configured to swallow one or more clock cycles of the first clock signal in generating the second clock signal. The first clock signal has even cycles, and the second clock signal has uneven cycles. The first frequency is greater than the second frequency. The module may include a cycle-swallowing counter. A method and a computer-readable medium are also provided.
摘要翻译：提供一种电子设备，用于产生或利用一个或多个基于一个或多个第一时钟信号导出的周期吞咽时钟信号。该设备包括被配置为接收具有第一频率的第一时钟信号的模块。该模块被配置为产生具有第二频率的第二时钟信号，并且被配置为在生成第二时钟信号时吞咽第一时钟信号的一个或多个时钟周期。第一个时钟信号具有偶数周期，第二个时钟信号具有不均匀的周期。第一个频率大于第二个频率。模块可以包括循环吞咽计数器。还提供了一种方法和计算机可读介质。

24. 发明申请

US20090086864A1 INTERFERENCE DETECTION AND MITIGATION 有权
公开(公告)号：US20090086864A1
公开(公告)日：2009-04-02
申请号：US12330813
申请日：2008-12-09
申请人： Christos Komninakis , Daniel F. Filipovic
发明人： Christos Komninakis , Daniel F. Filipovic
IPC分类号： H04B1/10 , H04B1/12
CPC分类号： H04B1/10 , H04B1/109 , H04B1/525
摘要： Techniques for detecting and mitigating interference are described. A device (e.g., a cellular phone) senses interference levels and digitally reconstructs the expected interference in the received signal. The device may correlate the reconstructed interference with the received signal and determine interference in the received signal based on correlation results. The device may adjust the operation of one or more circuit blocks (e.g., a mixer, an LNA, etc.) in a receiver based on the detected interference in the received signal. Alternatively or additionally, the device may condition the digital interference to obtain conditioned reconstructed interference matching the interference in the received signal and may then subtract the conditioned interference from the received signal.

25. 发明授权

US06812544B2 Integrated circuit having oversized components 有权
公开(公告)号：US06812544B2
公开(公告)日：2004-11-02
申请号：US10395430
申请日：2003-03-24
申请人： Harry Contopanagos , Christos Komninakis
发明人： Harry Contopanagos , Christos Komninakis
IPC分类号： H01L2900
CPC分类号： H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes electrical components that include one or more electrical elements on one or more dielectric layers. The electrical element has a geometric shape that exceeds prescribed integrated circuit manufacturing limits in at least one dimension. To achieve compliance with foundry rules, the electrical element is fabricated to include a non-conducting region that negligibly effects the electrical characteristics. The non-conducting region includes a hole, a series of holes, a slot and/or a series of slots spaced within the electrical element at dimensions that are less than the integrated circuit manufacturing limits.

26. 发明授权

US06709977B2 Integrated circuit having oversized components and method of manafacture thereof 有权
标题翻译：具有超大元件的集成电路及其制造方法
公开(公告)号：US06709977B2
公开(公告)日：2004-03-23
申请号：US10074515
申请日：2002-02-12
申请人： Harry Contopanagos , Christos Komninakis
发明人： Harry Contopanagos , Christos Komninakis
IPC分类号： H01L2144
CPC分类号： H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes electrical components that include one or more electrical elements on one or more dielectric layers. The electrical element has a geometric shape that exceeds prescribed integrated circuit manufacturing limits in at least one dimension. To achieve compliance with foundry rules, the electrical element is fabricated to include a non-conducting region that negligibly effects the electrical characteristics. The non-conducting region includes a hole, a series of holes, a slot and/or a series of slots spaced within the electrical element at dimensions that are less than the integrated circuit manufacturing limits.
摘要翻译：集成电路包括在一个或多个介电层上包括一个或多个电气元件的电气部件。电气元件具有在至少一个维度上超过规定的集成电路制造限制的几何形状。为了实现符合铸造规则，电气元件被制造成包括可忽略地影响电特性的非导电区域。非导电区域包括在小于集成电路制造限制的尺寸下在电气元件内间隔开的孔，一系列孔，槽和/或一系列槽。

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