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21. 发明授权

US07149107B2 Providing a reference voltage to a cross point memory array 有权
公开(公告)号：US07149107B2
公开(公告)日：2006-12-12
申请号：US11288472
申请日：2005-11-28
申请人： Darrell Rinerson , Christophe Chevallier
发明人： Darrell Rinerson , Christophe Chevallier
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C5/147 , G11C11/15 , G11C13/0004 , G11C2213/31
摘要： Providing a reference voltage to a cross point memory array. The invention is a cross point memory array and some peripheral circuitry that, when activated, provides a reference voltage to a cross point array. The peripheral circuitry can be activated before, after or during selection of a specific memory plug. If the peripheral circuitry is activated during selection, only the unselected conductive array lines should be brought to the reference voltage. Otherwise, all the conductive array lines can be brought to the reference voltage.

22. 发明申请

US20060181930A1 Erase verify for non-volatile memory 有权
标题翻译：擦除非易失性存储器的验证
公开(公告)号：US20060181930A1
公开(公告)日：2006-08-17
申请号：US11400993
申请日：2006-04-10
申请人： Christophe Chevallier
发明人： Christophe Chevallier
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C16/344
摘要： A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predetermined upper and lower limits. The verify circuit can include first and second comparators. In one embodiment, the first comparator is used to compare a bit line current with an upper first reference current. The second comparator is used to compare a bit line current with a lower second reference current. The comparator circuit is not limited to reference currents, but can use reference voltages to compare to a bit line voltage. The verify circuit, therefore, eliminates the need for separate bit line leakage testing to identify over-erased memory cells.
摘要翻译：存储器件验证系统确定存储器中存储器单元的状态。存储器包括具有耦合到位线的多个存储器单元的存储器阵列。验证电路耦合到位线以确定存储器单元是否具有在预定的上限和下限内的擦除电平。验证电路可以包括第一和第二比较器。在一个实施例中，第一比较器用于比较位线电流和较高的第一参考电流。第二比较器用于将位线电流与较低的第二参考电流进行比较。比较器电路不限于参考电流，但可以使用参考电压与位线电压进行比较。因此，验证电路不需要单独的位线泄漏测试来识别过度擦除的存储器单元。

23. 发明授权

US07082052B2 Multi-resistive state element with reactive metal 有权
标题翻译：具有反应性金属的多电阻状态元件
公开(公告)号：US07082052B2
公开(公告)日：2006-07-25
申请号：US10773549
申请日：2004-02-06
申请人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
发明人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
IPC分类号： G11C11/14
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
摘要翻译：提供经处理的导电元件。可以通过在导电元件上沉积反应性金属或非常薄的材料层来处理导电元件。反应性金属（或非常薄的材料层）通常将夹在导电元件和电极之间。该结构还具有非线性IV特性，这在某些阵列中是有利的。

24. 发明授权

US07032199B2 Design rule checking integrated circuits 失效
标题翻译：设计规则检查集成电路
公开(公告)号：US07032199B2
公开(公告)日：2006-04-18
申请号：US10781964
申请日：2004-02-19
申请人： Christophe Chevallier , Adriana Ababei
发明人： Christophe Chevallier , Adriana Ababei
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of design rule checking an integrated circuit identifies any line having a line width marker and line width parameter, extracts each line having a line width marker, determines the line width parameter for each extracted line, and compares the line width parameter with an actual line width for the line.
摘要翻译：设计规则检查集成电路的方法识别具有线宽标记和线宽参数的任何线，提取具有线宽标记的每条线，确定每条提取线的线宽参数，并将线宽参数与实际线宽线。

25. 发明申请

US20050270839A1 Erase verify for non-volatile memory 有权
公开(公告)号：US20050270839A1
公开(公告)日：2005-12-08
申请号：US11198212
申请日：2005-08-05
申请人： Christophe Chevallier
发明人： Christophe Chevallier
IPC分类号： G11C16/34 , G11C11/34
CPC分类号： G11C16/3404 , G11C16/344
摘要： A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predetermined upper and lower limits. The verify circuit can include first and second comparators. In one embodiment, the first comparator is used to compare a bit line current with an upper first reference current. The second comparator is used to compare a bit line current with a lower second reference current. The comparator circuit is not limited to reference currents, but can use reference voltages to compare to a bit line voltage. The verify circuit, therefore, eliminates the need for separate bit line leakage testing to identify over-erased memory cells.

26. 发明申请

US20050231992A1 Re-writable memory with multiple memory layers 有权
标题翻译：具有多个内存层的可重写内存
公开(公告)号：US20050231992A1
公开(公告)日：2005-10-20
申请号：US11151880
申请日：2005-06-13
申请人： Darrell Rinerson , Christophe Chevallier , Wayne Kinney , Steven Longcor , Edmond Ward
发明人： Darrell Rinerson , Christophe Chevallier , Wayne Kinney , Steven Longcor , Edmond Ward
IPC分类号： G11C11/56 , G11C13/00 , G11C16/02 , H01L27/24 , G11C5/00
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C2213/31
摘要： A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminals selected. Sharing logic over multiple layers allows driver sets to be reused.
摘要翻译：具有多个内存层的可重写内存。只要存在只有一个选择了两个端子的存储单元，就可以选择使用层叠交叉点结构中的存储单元的两个端子进行选择，以便选择多层导电线。通过多层共享逻辑可以重新使用驱动程序集。

27. 发明授权

US06940780B2 Flash array implementation with local and global bit lines 有权
公开(公告)号：US06940780B2
公开(公告)日：2005-09-06
申请号：US10784688
申请日：2004-02-23
申请人： Christophe Chevallier
发明人： Christophe Chevallier
IPC分类号： G11C7/18 , G11C29/02 , H01L27/115 , H01L11/401
CPC分类号： G11C29/025 , G11C7/18 , G11C29/02 , H01L27/115
摘要： A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.

28. 发明申请

US20050190638A1 Segmented non-volatile memory array with multiple sources having improved source line decode circuitry 审中-公开
标题翻译：具有多个源的分段非易失性存储器阵列具有改进的源极线解码电路
公开(公告)号：US20050190638A1
公开(公告)日：2005-09-01
申请号：US11103988
申请日：2005-04-12
申请人： Christophe Chevallier , Vinod Lakhani
发明人： Christophe Chevallier , Vinod Lakhani
IPC分类号： G11C16/08 , H01L27/115 , G11C16/04
CPC分类号： H01L27/115 , G11C16/08
摘要： A flash memory array arrangement having a plurality of erase blocks which can be separately erased. The erase blocks have separate source lines, the state of which is controlled by a source line decoder. In array read, program and erase operations, the source lines of the deselected erase blocks, the blocks that are not being read, programmed or erased, are set to a high impedance level. If a cell in one of the deselected erase blocks is defective in some respect such that the cell is conducting leakage current, the high impedance source line associated with the cell will reduce the likelihood that the defective cell will prevent proper operation of the selected erase block.
摘要翻译：一种闪存阵列装置，具有可以单独擦除的多个擦除块。擦除块具有分离的源极线，其状态由源极线解码器控制。在阵列读取，编程和擦除操作中，未选择的擦除块的源线，未被读取，编程或擦除的块被设置为高阻抗级。如果一个取消选择的擦除块中的单元在某些方面是有缺陷的，使得单元导致漏电流，则与单元相关联的高阻抗源极线将降低有缺陷单元将阻止所选擦除块的正确操作的可能性。

29. 发明申请

US20050174872A1 Line drivers that fits within a specified line pitch 失效
标题翻译：适用于指定线路间距的线路驱动器
公开(公告)号：US20050174872A1
公开(公告)日：2005-08-11
申请号：US11024279
申请日：2005-04-14
申请人： Darrell Rinerson , Christophe Chevallier
发明人： Darrell Rinerson , Christophe Chevallier
IPC分类号： G11C11/56 , G11C13/00 , G11C5/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C2213/31 , G11C2213/77
摘要： Line drivers that fit within a specified line pitch. One method of placing line drivers completely underneath a cross point array requires splitting the line driver up so that a portion of the line drivers is on a first side of the cross point array and the other portion is on the opposite side. However, using this technique requires that the width of the drivers is no larger than the width of the memory cells that are being driven. This can be accomplished by stacking transistors such that line drivers fit within a specified line pitch, but are as long as is necessary to include all the necessary circuitry.
摘要翻译：适合指定线路间距的线路驱动器。将线驱动器完全放置在交叉点阵列下方的一种方法需要将线驱动器向上分开，使得线驱动器的一部分位于交叉点阵列的第一侧，而另一部分在相对侧。然而，使用这种技术要求驱动器的宽度不大于被驱动的存储单元的宽度。这可以通过堆叠晶体管来实现，使得线路驱动器适合指定的线间距，但是必须包括所有必要的电路。

30. 发明申请

US20050018516A1 Discharge of conductive array lines in fast memory 有权
标题翻译：导电阵列线在快速存储器中放电
公开(公告)号：US20050018516A1
公开(公告)日：2005-01-27
申请号：US10922202
申请日：2004-08-18
申请人： Christophe Chevallier , Darrell Rinerson
发明人： Christophe Chevallier , Darrell Rinerson
IPC分类号： G11C11/56 , G11C13/00 , G11C16/02 , H01L27/22 , H01L27/24 , G11C7/00
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C2213/31 , G11C2213/72 , G11C2213/74 , G11C2213/76
摘要： Circuitry that discharges conductive array lines is provided. Generally, the conductive array lines are simultaneously selected and apply an appropriate programming pulse. Accordingly, the conductive array lines need to be discharged in connection with a write operation. The discharge can occur either prior to or following a write operation.
摘要翻译：提供放电导电阵列线路的电路。通常，同时选择导电阵列线并施加适当的编程脉冲。因此，导电阵列线需要与写入操作相关地放电。放电可以在写入操作之前或之后发生。

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