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    • 26. 发明授权
    • Cache memory control method and apparatus, and method and apparatus for
controlling memory capable of interleave control
    • 高速缓冲存储器控制方法和装置,以及用于控制能够进行交织控制的存储器的方法和装置
    • US5761695A
    • 1998-06-02
    • US714393
    • 1996-09-16
    • Takeshi MaedaAtsuhiro HigaKenichi Nagashima
    • Takeshi MaedaAtsuhiro HigaKenichi Nagashima
    • G06F12/06G06F12/08G06F13/00G06F12/00
    • G06F12/0607G06F12/0851G06F12/0893Y02B60/1225
    • In a memory control apparatus which has a main memory constructed by a plurality of memory areas and a cache memory which can be accessed at a speed higher than that of the main memory and in which the main memory or the cache memory is accessed in response to a memory access request from an access request side and data is read out and transferred to the access request side, an accessing speed of every plurality of memory areas in the main memory is identified and an area that is cachable for the cache memory among the plurality of memory areas in the main memory is set in accordance with the identified accessing speed of every plurality of memory areas in the main memory. In a memory control apparatus for performing an interleave access or a non-interleave access to an information memory medium having a plurality of banks of different capacities, a boundary address indicative of a boundary between the interleave access area and the non-interleave access area is compared with an access address to the information memory medium, and on the basis of the comparison result, the interleave access or non-interleave access is executed to the information memory medium.
    • 在具有由多个存储区域构成的主存储器和可以以比主存储器高的速度访问的高速缓冲存储器的存储器控​​制装置中,其中主存储器或高速缓存存储器响应于 来自访问请求侧的存储器访问请求和数据被读出并被传送到访问请求侧,识别主存储器中的每个多个存储区域的访问速度以及可以在多个存储器中高速缓冲存储器可高速缓存的区域 根据主存储器中每个多个存储区域的识别访问速度来设置主存储器中的存储区域。 在用于执行对具有不同容量的多个存储体的信息存储介质的交织访问或非交织访问的存储器控​​制装置中,指示交织访问区域和非交织访问区域之间的边界的边界地址是 与信息存储介质的访问地址进行比较,并且基于比较结果,对信息存储介质执行交织访问或非交织访问。