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21. 发明授权

US06897514B2 Two mask floating gate EEPROM and method of making 失效
标题翻译：两个掩模浮栅EEPROM及其制作方法
公开(公告)号：US06897514B2
公开(公告)日：2005-05-24
申请号：US10066376
申请日：2002-02-05
申请人： Igor G. Kouznetsov , Andrew J. Walker
发明人： Igor G. Kouznetsov , Andrew J. Walker
IPC分类号： H01L27/06 , H01L27/112 , H01L27/12 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/861 , H01L29/76
CPC分类号： H01L29/7926 , H01L27/0688 , H01L27/112 , H01L27/12 , H01L29/42324 , H01L29/7881 , H01L29/792 , H01L29/8616
摘要： There is provided a floating gate transistor, such as an EEPROM transistor, and method of making the transistor using two masking steps. The method of making a transistor includes patterning a floating gate layer using a first photoresist mask to form a floating gate rail and doping an active area using the floating gate rail as a mask to form source and drain regions in the active area. The method also includes patterning a control gate layer, a control gate dielectric layer, the floating gate rail, a tunnel dielectric layer and the active area using a second photoresist mask to form a control gate, a control gate dielectric, a floating gate, a tunnel dielectric and a channel island region.
摘要翻译：提供了诸如EEPROM晶体管的浮动栅极晶体管，以及使用两个掩模步骤制造晶体管的方法。制造晶体管的方法包括使用第一光致抗蚀剂掩模图案化浮栅，以形成浮栅，并且使用浮置栅极作为掩模掺杂有源区，以在有源区中形成源区和漏区。该方法还包括使用第二光致抗蚀剂掩模来形成控制栅极层，控制栅极介电层，浮动栅极轨道，隧道介电层和有源区域以形成控制栅极，控制栅极电介质，浮动栅极，隧道电介质和沟道岛区。

22. 发明授权

US06859410B2 Tree decoder structure particularly well-suited to interfacing array lines having extremely small layout pitch 有权
标题翻译：树解码器结构特别适合于具有非常小的布局间距的阵列线的接口
公开(公告)号：US06859410B2
公开(公告)日：2005-02-22
申请号：US10306888
申请日：2002-11-27
申请人： Roy E. Scheuerlein , Matthew P. Crowley
发明人： Roy E. Scheuerlein , Matthew P. Crowley
IPC分类号： G11C5/02 , G11C8/10 , G11C8/00
CPC分类号： G11C8/10 , G11C5/025
摘要： A tree decoder organization particularly useful for a three-dimensional memory array or any array having very small array line pitch is configured to provide a plurality of top-level decode nodes, each of which, when selected, simultaneously selects a block of array lines and couples each array line of a selected block to a respective intermediate node. Each of the top-level decode signals has a range of control which is substantially less than the extent of the intermediate nodes. In some embodiments each selected block includes more than one array line on each of at least two memory layers having array lines which exit to one side of the memory array. As a result, the large layout area requirement to generate each top-level decode node is supported by a contiguous block of array lines of the memory array.
摘要翻译：特别适用于三维存储器阵列或具有非常小的阵列线间距的任何阵列的树解码器组合被配置为提供多个顶级解码节点，每个顶级解码节点当被选择时同时选择阵列线块，并且将所选块的每个阵列线耦合到相应的中间节点。每个顶层解码信号都具有一个大大小于中间节点范围的控制范围。在一些实施例中，每个所选择的块包括至少两个存储器层中的每一个具有排列到存储器阵列的一侧的阵列线的多于一个阵列线。结果，生成每个顶层解码节点的大布局面积要求由存储器阵列的连续阵列线支持。

23. 发明申请

US20050026334A1 Vertically stacked, field programmable, nonvolatile memory and method of fabrication 有权
标题翻译：垂直堆叠，现场可编程，非易失性存储器和制造方法
公开(公告)号：US20050026334A1
公开(公告)日：2005-02-03
申请号：US10848601
申请日：2004-05-17
申请人： Johan Knall
发明人： Johan Knall
IPC分类号： G11C17/16 , H01L21/82
CPC分类号： G11C17/16
摘要： A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer. The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by the anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.
摘要翻译：三维现场可编程的非易失性存储器包括多层第一和第二交叉导体。支柱在相邻的第一和第二交叉导体的交叉处自对准，并且每个柱包括至少一个抗熔合层。支柱与相邻的导体形成存储器单元，并且每个存储单元包括由反熔丝层分离的第一和第二二极管部件。仅在反熔丝层中断之后，二极管组件才形成二极管。

24. 发明授权

US06843421B2 Molded memory module and method of making the module absent a substrate support 有权
标题翻译：模制记忆模块和使模块不存在衬底支撑的方法
公开(公告)号：US06843421B2
公开(公告)日：2005-01-18
申请号：US09928767
申请日：2001-08-13
申请人： Khushrav S. Chhor , Larry L. Moresco
发明人： Khushrav S. Chhor , Larry L. Moresco
IPC分类号： G06K19/077 , G06K19/06
CPC分类号： G06K19/07743 , G06K19/07745 , H01L24/73 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/49113 , H01L2224/73265 , H01L2225/06562 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/14 , H01L2924/19041 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： An improved memory module and method of manufacture are presented. The memory module takes on the same outer dimensions as conventional memory cards. The memory module includes an integrated circuit and a conductor encased within molded resin. The conductor can be taken from a tape or a lead frame, and can include bumps or wires extending from the conductor to corresponding bonding pads on the integrated circuit. The bonded integrated circuit can thereafter be placed within a cavity formed inside a mold housing, where resin may be injected to form the memory module. The conductor can also be shaped so as to extend on multiple planes from the connection point on or near the bonding pad to an edge connector residing near one edge only of the memory module. The conductor is thereby connected to the integrated circuit and provides slide-in, releasable coupling to a receptor.
摘要翻译：提出了一种改进的存储器模块和制造方法。内存模块采用与传统存储卡相同的外部尺寸。存储器模块包括集成电路和封装在模制树脂内的导体。导体可以从带子或引线框架中取出，并且可以包括从导体延伸到集成电路上的相应接合焊盘的凸起或电线。接合的集成电路此后可以放置在形成在模具外壳内的空腔中，其中树脂可被注入以形成存储器模块。导体还可以成形为在多个平面上从接合焊盘上或附近的连接点延伸到仅位于存储器模块的一个边缘附近的边缘连接器。因此，导体连接到集成电路并且提供滑入式可释放耦合到接收器。

25. 发明申请

US20040262702A1 Low-density, high-resistivity titanium nitride layer for use as a contact for low-leakage dielectric layers 有权
标题翻译：低密度，高电阻率氮化钛层，用作低漏电介质层的接触
公开(公告)号：US20040262702A1
公开(公告)日：2004-12-30
申请号：US10611245
申请日：2003-06-30
申请人： MATRIX SEMICONDUCTOR, INC.
发明人： S. Brad Herner
IPC分类号： H01L029/76
CPC分类号： H01L23/5252 , H01L21/28088 , H01L21/28273 , H01L21/28282 , H01L21/2855 , H01L21/3205 , H01L28/60 , H01L29/4966 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A low-density, high-resistivity layer of a PVD sputter-deposited material, preferably titanium nitride, when coupled with a dielectric, makes a superior low-leakage insulating barrier for use in semiconductor devices. The material is created by sputtering methods that cause the ions to strike the deposition surface with reduced energy, for example in an ion metal plasma chamber with no self-bias accelerating ions normal to the deposition surface, or in a standard PVD chamber with pressure increased.
摘要翻译：当与电介质耦合时，PVD溅射沉积材料（优选氮化钛）的低密度，高电阻率层产生用于半导体器件的优异的低漏电绝缘屏障。该材料是通过溅射方法产生的，这些方法使离子以较低的能量冲击沉积表面，例如在离子金属等离子体室中，没有自偏压加速垂直于沉积表面的离子，或者在具有压力增加的标准PVD室中。

26. 发明申请

US20040232509A1 Rail schottky device and method of making 有权
标题翻译：轨道肖特基装置及其制造方法
公开(公告)号：US20040232509A1
公开(公告)日：2004-11-25
申请号：US10440882
申请日：2003-05-19
申请人： MATRIX SEMICONDUCTOR, Inc.
发明人： Michael A. Vyvoda
IPC分类号： H01L027/095
CPC分类号： H01L23/5252 , H01L27/1021 , H01L2924/0002 , Y10S257/91 , H01L2924/00
摘要： A monolithic three dimensional memory array comprising Schottky diodes components separated by antifuses is disclosed. The Schottky diodes are vertically oriented and disposed on alternating levels. Those on odd levels are nullrightside-upnull with antifuse over the metal, and those on even levels are nullupside downnull with metal over the antifuse. Both antifuses are preferably grown oxides.
摘要翻译：公开了包括由反熔丝分离的肖特基二极管部件的单片三维存储器阵列。肖特基二极管是垂直取向的并且设置在交替的电平上。那些在奇怪的层面上是金属上的反熔丝是“右起”的，而平均层次上的那些是反金属的“颠倒”的。两种反熔点优选是生长的氧化物。

27. 发明申请

US20040206996A1 Dense arrays and charge storage devices 有权
标题翻译：密集阵列和电荷存储设备
公开(公告)号：US20040206996A1
公开(公告)日：2004-10-21
申请号：US10842008
申请日：2004-05-10
申请人： Matrix Semiconductor, Inc.
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
IPC分类号： H01L021/8242
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

28. 发明申请

US20030206429A2 VERTICALLY STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF FABRICATION 有权
标题翻译：垂直堆叠现场可编程非易失性存储器和制造方法
公开(公告)号：US20030206429A2
公开(公告)日：2003-11-06
申请号：US09939498
申请日：2001-08-24
申请人： Matrix Semiconductor, Inc.
发明人： Vivek Subramanian , James M. Cleeves
IPC分类号： G11C017/00
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： Abstract of DisclosureA very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with Nnull1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要翻译：公开摘要公开了一种非常高密度的现场可编程存储器。阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。自动对准技术的最大限度地使光刻限制最小化。在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

29. 发明申请

US20030202404A1 Memory device with row and column decoder circuits arranged in a checkboard pattern under a plurality of memory arrays 有权
标题翻译：具有排列在多个存储器阵列下的棋盘图案中的行和列解码器电路的存储器件
公开(公告)号：US20030202404A1
公开(公告)日：2003-10-30
申请号：US10440377
申请日：2003-05-16
申请人： Matrix Semiconductor, Inc.
发明人： Roy E. Scheuerlein
IPC分类号： G11C005/02
CPC分类号： G11C8/10 , G11C5/025 , G11C7/062 , G11C7/067 , G11C7/18 , G11C8/08 , G11C17/18 , G11C2207/063
摘要： The preferred embodiments described herein provide a memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. In one preferred embodiment, a memory device is provided with its row decoder circuits and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. Because each of the row decoder and column decoder circuits is associated with the memory array above its location and an adjacent array, a denser support circuit arrangement is provided as compared to prior approaches. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.
摘要翻译：本文描述的优选实施例提供了一种存储器件，其具有在多个存储器阵列下以棋盘图案布置的行和列解码器电路。在一个优选实施例中，存储器件具有其排列在多个存储器阵列下的棋盘图案中的行解码器电路和列解码器电路。因为行解码器和列解码器电路中的每一个都与其位置上方的存储器阵列和相邻阵列相关联，所以与现有方法相比，提供了更密集的支持电路装置。提供了其它优选实施方案，并且本文所述的各优选实施方案可以单独使用或彼此组合使用。

30. 发明申请

US20030057435A1 Thin film transistors with vertically offset drain regions 有权
标题翻译：具有垂直偏移漏极区域的薄膜晶体管
公开(公告)号：US20030057435A1
公开(公告)日：2003-03-27
申请号：US09961278
申请日：2001-09-25
申请人： Matrix Semiconductor, Inc.
发明人： Andrew J. Walker
IPC分类号： H01L029/74
CPC分类号： H01L27/112 , H01L27/0688 , H01L27/12
摘要： There is provided a semiconductor device, such as a TFT, with a vertical drain offset region. The device contains a substrate having an upper first surface, a semiconductor channel region of a first conductivity type over the first surface, a gate electrode and a gate insulating layer between the gate electrode and the channel region. The device also contains a heavily doped semiconductor source region of a second conductivity type, a heavily doped semiconductor drain region of a second conductivity type. An intrinsic or lightly doped semiconductor drain offset region is located between the drain region and the channel region, such that the drain region is offset from the channel region at least partially in a direction perpendicular to the first surface.
摘要翻译：提供了具有垂直漏极偏移区域的诸如TFT的半导体器件。该器件包含具有上部第一表面，第一表面上的第一导电类型的半导体沟道区，栅电极和栅极电极与沟道区之间的栅极绝缘层的衬底。该器件还包含第二导电类型的重掺杂半导体源极区域，第二导电类型的重掺杂半导体漏极区域。本征或轻掺杂的半导体漏极偏移区域位于漏极区域和沟道区域之间，使得漏极区域至少部分地在垂直于第一表面的方向上偏离沟道区域。

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