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11. 发明授权

US11791831B1 Modular redundant threshold circuit and method 有权
公开(公告)号：US11791831B1
公开(公告)日：2023-10-17
申请号：US18320644
申请日：2023-05-19
申请人： Apogee Semiconductor, Inc.
发明人： David A. Grant , Mark Hamlyn
IPC分类号： H03M7/00 , H03M7/34 , H03M1/12 , H03M1/06 , H03K19/08 , H03K19/23
CPC分类号： H03M1/0687 , H03K19/0813 , H03K19/23
摘要： Systems and methods for fault-tolerant threshold circuits used in converting an analog input to a single-bit digital output employ N-modular redundancy of either inverting or non-inverting threshold circuits whose inputs are connected to a single input, and apply majority voting of their outputs to provide correction of transient or permanent faults in up to floor[(N−1)/2] of the individual threshold circuits. Using summation to perform analog majority voting averages the N threshold circuit outputs and provides resilience to single-event transients, but may exhibit an output characteristic having intermediate voltage levels. A digital majority voter having N inputs connected to the outputs of N threshold circuits restores well-defined logic levels and clean hysteresis for Schmitt trigger threshold circuits. A single point of failure at the digital majority voter may be eliminated using an analog majority voter to sum the outputs of three or more redundant digital majority voters.

12. 发明授权

US11784654B2 Digital-to-analog conversion apparatus and method having signal calibration mechanism 有权
公开(公告)号：US11784654B2
公开(公告)日：2023-10-10
申请号：US17691502
申请日：2022-03-10
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Hsuan-Ting Ho , Shih-Hsiung Huang , Liang-Wei Huang
IPC分类号： H03M1/10 , H03M7/00 , H03M1/66
CPC分类号： H03M1/1009 , H03M1/1071 , H03M1/10 , H03M1/66 , H03M7/00
摘要： The present invention discloses a DAC method having signal calibration mechanism. A first conversion circuit generates a first analog signal according to an input digital signal. A second conversion circuit generates a second analog signal according to the input digital signal and a pseudo-noise digital signal. An echo transmission circuit processes a signal on an echo path to generate an echo signal. A first and a second calibration circuits generate a first and a second calibration signals. A calibration parameter calculation circuit performs calculation according to a difference between the echo signal and a sum of the first and the second calibration signals and related path information to generate a first and a second offsets. The first and the second calibration circuits converge first and second response coefficients and update a first and a second codeword offset tables according to the first and the second offsets.

13. 发明授权

US11783370B2 Graph-based compression of data records 有权
公开(公告)号：US11783370B2
公开(公告)日：2023-10-10
申请号：US17819511
申请日：2022-08-12
申请人： Groupon, Inc.
发明人： Ricardo A. Zilleruelo-Ramos , Hernan Enrique Arroyo Garcia , Joe Frisbie , Gaston L'Huillier , Francisco Jose Larrain
IPC分类号： H03M7/00 , G06Q30/0242 , H03M7/30 , G06F16/951 , G06F16/174 , G06F16/22 , G06F16/955
CPC分类号： G06Q30/0246 , G06F16/1744 , G06F16/2282 , G06F16/951 , G06F16/955 , H03M7/30 , H03M7/70
摘要： In general, embodiments of the present invention provide systems, methods and computer readable media for data record compression using graph-based techniques. An example method includes determining a plurality of index components; generating a sorted data record list of a plurality of compound data records; generating an ordered unique index component value list associated with a plurality of unique index component values; assigning a plurality of encodings to the plurality of unique index component values; and generating the compressed data record list based on the ordered unique index component value list and the plurality of encodings.

14. 发明授权

US11687792B2 Cyphergenics-based decoding and encoding of executable instructions 有权
公开(公告)号：US11687792B2
公开(公告)日：2023-06-27
申请号：US17668929
申请日：2022-02-10
申请人： Quantum Digital Solutions Corporation
发明人： William C. Johnson , Karen Ispiryan , Gurgen Khachatryan
IPC分类号： G06N3/126 , G16B30/20 , G16B50/30 , G06F21/53 , G16B99/00 , G16B50/50 , G16B30/00 , H04L9/06 , H04L9/32 , H04L9/00 , H03M7/00
CPC分类号： G06N3/126 , G06F21/53 , G16B30/00 , G16B30/20 , G16B50/30 , G16B50/50 , G16B99/00 , H03M7/00 , H04L9/002 , H04L9/0643 , H04L9/3247 , H04L9/50 , G06F2221/2149
摘要： A method for executing computer programs in a trusted execution environment of a device is disclosed. The method includes retrieving a genomic differentiation object corresponding to a computer program that comprises a set of encoded executable instructions. The method further includes modifying the genomic differentiation object based on genomic regulation instructions (GRI) to obtain a modified genomic differentiation object, wherein the GRI were used to encode the set of encoded executable instructions of the computer program. The method includes obtaining a first instruction that is to be executed from the first set of encoded executable instructions of the computer program; obtaining a first sequence from first metadata associated with the first encoded instruction; generating a genomic engagement factor (GEF) based on the first sequence and the modified genomic differentiation object; decoding the first encoded instruction using the GEF to obtain a first decoded instruction; and executing the first decoded instruction.

15. 发明授权

US11637563B2 Decoding circuit and chip 有权
公开(公告)号：US11637563B2
公开(公告)日：2023-04-25
申请号：US17608302
申请日：2021-04-19
申请人： SHANGHAI XINLONG SEMICONDUCTOR TECHNOLOGY CO., LTD.
发明人： Ruiping Li , Wei Chi , Bin Liu , Jianhu Wang
IPC分类号： H03M7/00 , H03M7/30
摘要： A decoding circuit and a chip are disclosed. The decoding circuit includes, connected in a sequence, a charge/discharge unit, a capacitor and a conversion unit. The charge/discharge unit is able to charge and discharge the capacitor, and a ratio of a total time required to transfer any amount of charge into the capacitor to a total time required to transfer the same amount of charge from the capacitor is a predetermined value. The conversion unit is configured to output a third level when a voltage on the capacitor exceeds a predetermined voltage and to otherwise output a fourth level. This arrangement alleviates the computational burden of an MCU, eliminates any adverse effect of noise in a transmitted signal, allows an extended effective transmission distance when using an HBS protocol and is self-adaptive to signals transmitted at different clock rates, thus solving the problems with the prior art including heavy MCU computational burden, a tradeoff between error correction and transmission distance and insufficient adaptiveness to signals transmitted at different clock rates.

16. 发明授权

US11616513B2 Decoding apparatus, decoding method, and program 有权
公开(公告)号：US11616513B2
公开(公告)日：2023-03-28
申请号：US17254792
申请日：2019-04-25
申请人： Sony Corporation
发明人： Shuichiro Nishigori , Shiro Suzuki , Hirofumi Takeda , Jun Matsumoto
IPC分类号： H03M7/00 , H03M7/30 , G06F3/01
摘要： A tactile reproduction system achieves a data amount reduction of a tactile signal while ensuring reproducibility of a tactile sense. A decoding apparatus includes a decoding unit configured to decode tactile coded data obtained by performing encoding of compressing an information amount, on a tactile signal using higher-order perception in a tactile sense. Therefore, a data amount reduction of a tactile signal can be performed in accordance with a tactile characteristic of a human.

17. 发明授权

US11601135B2 Internet of things data compression system and method 有权
公开(公告)号：US11601135B2
公开(公告)日：2023-03-07
申请号：US16803484
申请日：2020-02-27
申请人： BTS Software Solutions, LLC
发明人： Dunling Li
IPC分类号： H03M7/00 , H03M7/40 , H03M7/46 , H03M7/30 , G16Y20/10
摘要： A disclosure for lossless data compression can include receiving a data block by a processor, performing, by the processor, a sparse transform extraction on the data block, selecting, by the processor, a transform matrix for the data block, modeling, by the processor, the selected transform matrix for the data block, selecting, by the processor, a transform coefficient model for the data block, modeling, by the processor, the selected transform coefficient model for the data block, compressing, by the processor, the data in the data block using the selected transform matrix and the selected transform coefficient model.

18. 发明申请

US20220376703A1 Compression And Decompression In Hardware for Data Processing 有权
公开(公告)号：US20220376703A1
公开(公告)日：2022-11-24
申请号：US17328452
申请日：2021-05-24
申请人： Google LLC
发明人： Reiner Alwyn Pope
IPC分类号： H03M7/42 , H03M7/30 , H03M7/00
摘要： Methods, systems, and apparatus, including computer-readable storage media for hardware compression and decompression. A system can include a decompressor device coupled to a memory device and a processor. The decompressor device can be configured to receive, from the memory device, compressed data that has been compressed using an entropy encoding, process the compressed data using the entropy encoding to generate uncompressed data, and send the uncompressed data to the processor. The system can also include a compressor device configured to generate, from uncompressed data, a probability distribution of codewords, generate a code table from the probability distribution, and compress incoming data using the generated code table.

19. 发明授权

US11489541B2 Compression techniques for data structures suitable for artificial neural networks 有权
公开(公告)号：US11489541B2
公开(公告)日：2022-11-01
申请号：US16426303
申请日：2019-05-30
申请人： Nvidia Corporation
发明人： Jorge Albericio Latorre , Ming Y. Siu
IPC分类号： H03M7/00 , H03M7/30 , G06N3/08
摘要： In artificial neural networks, and other similar applications, there is typically a large amount of data involved that is considered sparse data. Due to the large size of the data involved in such applications, it is helpful to compress the data to save bandwidth resources when transmitting the data and save memory resources when storing the data. Introduced herein is a compression technique that selects elements with significant values from data and restructures them into a structured sparse format. By generating metadata that enforces the structured sparse format and organizing the data according to the metadata, the introduced technique not only reduces the size of the data but also consistently places the data in a particular format. As such, hardware can be simplified and optimized to process the data much faster and much more efficiently than the conventional compression techniques that rely on a non-structured sparsity format.

20. 发明授权

US11456754B2 Fixed size soft bit lossy compression in flash memory 有权
公开(公告)号：US11456754B2
公开(公告)日：2022-09-27
申请号：US17177940
申请日：2021-02-17
申请人： Western Digital Technologies, Inc.
发明人： Ran Zamir , Eran Sharon , Idan Alrod , Alexander Bazarsky , Yan Li , A Harihara Sravan
IPC分类号： H03M7/00 , H03M7/30 , G06F12/08 , G06F11/00 , G11C16/26 , G11C11/56
摘要： A memory includes, in one embodiment, one or more storage elements; read/write circuitry; and compressed bit circuitry. The read/write circuitry is configured to read a set of hard bits from the one or more storage elements, and sense a set of soft bits while reading the set of hard bits from the one or more storage elements, the set of soft bits having a first fixed size, and the set of soft bits indicating a reliability of the set of hard bits. The compressed soft bit circuitry is configured to generate, with a fixed size soft bit lossy compression algorithm, a fixed size compressed soft bits by compressing the set of soft bits, the fixed size compressed soft bits having a second fixed size that is smaller than the first fixed size, and output the fixed size compressed soft bits to a memory-to-controller bus.

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