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11. 发明申请

US20040238808A1 Transistor with an electron and a vertical channel and production methods thereof 失效
标题翻译：具有电子和垂直通道的晶体管及其制造方法
公开(公告)号：US20040238808A1
公开(公告)日：2004-12-02
申请号：US10491265
申请日：2004-03-30
发明人： David Fraboulet , Simon Deleonibus
IPC分类号： H01L029/06 , H01L039/00 , H01L031/036 , H01L021/335 , H01L021/00
CPC分类号： H01L29/0895 , B82Y10/00 , H01L29/66439 , H01L29/7613 , H01L49/006 , Y10S438/962
摘要： This invention relates to a Coulomb blockade transistor comprising the following on a substrate: a stack of channel layers (22c, 22i) forming at least one quantum box, a source (12) and a drain (80) connected to the quantum box through tunnel junctions, and stacked with the channel layers, at least one grid (60) facing at least one flank of the stack.
摘要翻译：本发明涉及一种库仑阻塞晶体管，其在衬底上包括以下部分：形成至少一个量子箱的沟道层叠层（22c，22i），通过隧道连接到量子盒的源极（12）和漏极（80）并且与通道层堆叠，至少一个面向堆叠的至少一个侧面的格栅（60）。

12. 发明申请

US20040209405A1 Liquid crystal display device 有权
标题翻译：液晶显示装置
公开(公告)号：US20040209405A1
公开(公告)日：2004-10-21
申请号：US10845220
申请日：2004-05-14
申请人： LG. Philips LCD Co., Ltd.
发明人： Dong Yeung Kwak , Gun Hee Lee
IPC分类号： H01L021/335
CPC分类号： G02F1/1345 , G02F1/136227
摘要： A liquid crystal display device is provided wherein an adhesive force between a seal and a lower plate is improved upon bonding of an upper plate to the lower plate. In high aperture liquid crystal display panels, organic protective films are used to reduce dielectric constants. However, the seal, used when bonding the upper and lower plates of the liquid crystal panel, generally do not adhere well to organic materials. In this invention, holes are generated in the organic protective film so that the seal bonds with inorganic materials such as the lower glass plate or the gate insulating film.
摘要翻译：提供了一种液晶显示装置，其中在将上板接合到下板时，密封件和下板之间的粘合力得到改善。在高孔径液晶显示面板中，使用有机保护膜来降低介电常数。然而，当粘合液晶面板的上板和下板时使用的密封通常不能很好地粘附到有机材料上。在本发明中，在有机保护膜中产生孔，使得密封与无机材料如下玻璃板或栅极绝缘膜接合。

13. 发明申请

US20040157380A1 Method for fabricating a MOSFET having a very small channel length 失效
标题翻译：用于制造具有非常小的沟道长度的MOSFET的方法
公开(公告)号：US20040157380A1
公开(公告)日：2004-08-12
申请号：US10673705
申请日：2003-09-26
发明人： Annalisa Cappellani , Ludwig Dittmar , Dirk Schumann
IPC分类号： H01L021/335
CPC分类号： H01L21/28114 , H01L21/2652 , H01L21/28052 , H01L21/28061 , H01L21/28123 , H01L21/32137 , H01L29/66575
摘要： A gate layer stack formed with at least two layers is firstly patterned anisotropically and then the lower layer is etched. An isotropic, preferably selective etching step effects a lateral undercutting, i.e. removal of the lower layer as far as the predetermined channel length. This allows a T-gate transistor with a very short channel length to be fabricated dimensionally accurately, in a simple manner and cost-effectively. Its electrical switching properties are better than those of other T-gate transistors formed by conventional methods.
摘要翻译：形成有至少两层的栅极层叠层首先被各向异性地图案化，然后蚀刻下层。各向同性，优选选择性蚀刻步骤会影响横向底切，即除去下层至预定通道长度。这允许以简单的方式和成本有效地尺寸精确地制造具有非常短的通道长度的T形栅极晶体管。其电开关特性优于常规方法形成的其他T型栅极晶体管。

14. 发明申请

US20040142514A1 Methods of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20040142514A1
公开(公告)日：2004-07-22
申请号：US10746805
申请日：2003-12-26
发明人： Byoung Yoon Seo , Teresa Lim
IPC分类号： H01L021/335
CPC分类号： H01L29/665 , H01L21/265 , H01L21/28518
摘要： Disclosed is an example method of manufacturing a semiconductor device. The disclosed example method includes depositing a gate insulating layer on an active region of a self aligned silicide (salicide) region and a non-self aligned silicide (salicide) region of a semiconductor substrate, forming a gate electrode, a poly crystal silicon layer, on the gate insulating layer of the self aligned silicide (salicide) region, and forming a spacer on both sidewalls of the gate electrode. The example method may further include depositing a silicide shielding layer on the gate insulating layer to cover the gate electrode and the spacer, forming a photoresist on the silicide shielding layer of the non-self aligned silicide (salicide) region, removing the silicide shielding layer of the self aligned silicide (salicide) region to expose the gate electrode, and performing an ion-implantation to render the poly crystal silicon layer of the gate electrode amorphous, without removing the photoresist on the silicide shielding layer of the non-self aligned silicide (salicide) region. The example method may further include removing the photoresist on the silicide shielding layer of the non-self aligned silicide (salicide) region and cleaning the semiconductor substrate and depositing a metal layer for forming a silicide layer and forming the silicide layer on the gate electrode of the self aligned silicide (salicide) region by annealing the semiconductor device.
摘要翻译：公开了制造半导体器件的示例性方法。所公开的示例方法包括在半导体衬底的自对准硅化物（自对准硅）区域和非自对准硅化物（自对准硅化物）区域的有源区上沉积栅极绝缘层，形成栅电极，多晶硅层，在自对准硅化物（硅化物）区域的栅极绝缘层上，并且在栅电极的两个侧壁上形成间隔物。示例性方法还可以包括在栅极绝缘层上沉积硅化物屏蔽层以覆盖栅电极和间隔物，在非自对准硅化物（硅化物）区的硅化物屏蔽层上形成光致抗蚀剂，去除硅化物屏蔽层的自对准硅化物（自对准硅化物）区域以露出栅电极，并且进行离子注入以使栅电极的多晶硅层无定形，而不去除非自对准硅化物的硅化物屏蔽层上的光致抗蚀剂（自杀）地区。该示例性方法还可以包括去除非自对准硅化物（硅化物）区域的硅化物屏蔽层上的光致抗蚀剂，并清洗半导体衬底并沉积用于形成硅化物层的金属层，并在栅电极上形成硅化物层通过退火半导体器件来自对准硅化物（自对准硅化物）区域。

15. 发明申请

US20040137667A1 Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20040137667A1
公开(公告)日：2004-07-15
申请号：US10475115
申请日：2003-10-17
发明人： Hisashi Ogawa , Hiroaki Nakaoka , Atsuhiro Kajiya , Shin Hashimoto , Kyoko Egashira
IPC分类号： H01L021/335
CPC分类号： H01L27/10852 , H01L27/0207 , H01L27/105 , H01L27/10894 , H01L27/10897
摘要： A memory cell transistor and a planar capacitor are provided in a memory region, and both transistors of a CMOS device are provided in a logic circuit region. A capacitance dielectric 15 and a plate electrode 16b of the planar capacitor are provided over a trench shared with a shallow trench isolation 12a, and the upper part of the trench is filled with the capacitance dielectric 15 and the plate electrode 16b. An n-type diffusion layer 19 that is a storage node is formed, with an end region thereof extending along one side of the upper part of the trench, to a region of the substrate overlapping with the shallow trench isolation 12a. The area of a part of the substrate functioning as a capacitor can be increased without increasing the substrate area.
摘要翻译：存储单元晶体管和平面电容器设置在存储区域中，CMOS器件的两个晶体管都设置在逻辑电路区域中。平面电容器的电容电介质15和平板电极16b设置在与浅沟槽隔离层12a共用的沟槽上，沟槽的上部填充有电容电介质15和平板电极16b。形成作为存储节点的n型扩散层19，其端部区域沿着沟槽的上部的一侧延伸到与浅沟槽隔离层12a重叠的区域。可以增加用作电容器的基板的一部分的面积，而不增加基板面积。

16. 发明申请

US20040132232A1 Vertical gain cell and array for a dynamic random access memory and method for forming the same 失效
公开(公告)号：US20040132232A1
公开(公告)日：2004-07-08
申请号：US10738449
申请日：2003-12-16
申请人： Micron Technology, Inc.
发明人： Wendell P. Noble
IPC分类号： H01L021/335
CPC分类号： H01L27/108 , H01L27/10841 , H01L27/10864
摘要： A vertical gain memory cell including an n-channel metal-oxide semiconductor field-effect transistor (MOSFET) and p-channel junction field-effect transistor (JFET) transistors formed in a vertical pillar of semiconductor material is provided. The body portion of the p-channel transistor is coupled to a second source/drain region of the MOSFET which serves as the gate for the JFET. The second source/drain region of the MOSFET is additionally coupled to a charge storage node. Together the second source/drain region and charge storage node provide a bias to the body of the JFET that varies as a function of the data stored by the memory cell. A non destructive read operation is achieved. The stored charge is sensed indirectly in that the stored charge modulates the conductivity of the JFET so that the JFET has a first turn-on threshold for a stored logic null1null condition and a second turn-on threshold for a stored logic null0null condition. The charge storage node is a plate capacitor which surrounds the second source/drain region of the MOSFET. The vertical gain cell is fabricated so that the write word line, read bit line, read word line and capacitor are buried beneath the silicon surface. As a result the cell can be fabricated in an area as small as four (4) lithographic feature squares.

17. 发明申请

US20040110324A1 Method of forming a negative differential resistance device 有权
标题翻译：形成负差动电阻装置的方法
公开(公告)号：US20040110324A1
公开(公告)日：2004-06-10
申请号：US10314735
申请日：2002-12-09
发明人： Tsu-Jae King
IPC分类号： H01L021/335
CPC分类号： H01L29/78 , H01L21/2652 , H01L21/823462 , H01L29/42332
摘要： A negative differential resistance (NDR) field-effect transistor element is disclosed, formed on a silicon-based substrate using conventional MOS manufacturing operations. Methods for improving a variety of NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters are also disclosed.
摘要翻译：公开了一种使用常规MOS制造操作在硅基衬底上形成的负差动电阻（NDR）场效应晶体管元件。还公开了用于改善NDR元件的各种NDR特性的方法，例如峰 - 谷比（PVR），NDR起始电压（VNDR）和相关参数。

18. 发明申请

US20040043542A1 Methods of forming self-aligned contact structures in semiconductor integrated circuit devices 有权
标题翻译：在半导体集成电路器件中形成自对准接触结构的方法
公开(公告)号：US20040043542A1
公开(公告)日：2004-03-04
申请号：US10656935
申请日：2003-09-05
发明人： Jong-Woo Park , Yun-Gi Kim , Dong-Gun Park
IPC分类号： H01L021/335
CPC分类号： H01L27/10855 , H01L21/76831 , H01L21/76897 , H01L27/10885
摘要： Methods of forming integrated circuit devices (e.g., memory devices) include the use of preferred self-aligned contact hole fabrication steps. These steps improve process reliability by reducing the likelihood that contact holes will become misaligned to underlying integrated circuit device structures and thereby potentially expose the structures in an adverse manner. Typical methods include the steps of forming a plurality of interconnection patterns on a substrate and then covering a surface of the interconnection patterns and a portion of the substrate with a capping insulating layer such as silicon nitride layer. The capping insulating layer is then covered with an upper interlayer insulating layer different from the capping insulating layer. The upper interlayer insulating layer and the capping insulating layer are then dry-etched in sequence to form a first narrow contact hole that exposes the substrate, but preferably does not expose the interconnection patterns. The first contact hole is then widened in a self-aligned manner using the capping insulating layer as an etch-stop layer. This widening step is performed by wet etching sidewalls of the first contact hole using an etchant that etches the upper interlayer insulating layer faster than the capping insulating layer. In this manner, the first contact hole may be formed to initially compensate for potential misalignment errors and then a self-aligned wet etching step may be performed to widen the first contact hole into a second contact hole so that low resistance contacts (e.g., contact plugs) can be provided therein.
摘要翻译：形成集成电路器件（例如，存储器件）的方法包括使用优选的自对准接触孔制造步骤。这些步骤通过减少接触孔将变得不对准到下面的集成电路器件结构并由此以不利的方式潜在地暴露结构的可能性来提高工艺可靠性。典型的方法包括以下步骤：在衬底上形成多个互连图案，然后用诸如氮化硅层的覆盖绝缘层覆盖互连图案的表面和衬底的一部分。然后用与封盖绝缘层不同的上层间绝缘层覆盖封盖绝缘层。然后依次对上层间绝缘层和封盖绝缘层进行干式蚀刻，形成露出基板的第一窄接触孔，但优选不暴露互连图案。然后使用封盖绝缘层作为蚀刻停止层，以自对准的方式加宽第一接触孔。通过使用蚀刻上层间绝缘层的蚀刻剂比封盖绝缘层更快地湿蚀刻第一接触孔的侧壁来进行该扩大步骤。以这种方式，可以形成第一接触孔以最初补偿潜在的未对准误差，然后可以执行自对准的湿蚀刻步骤，以将第一接触孔加宽成第二接触孔，使得低电阻接触（例如，接触插头）。

19. 发明申请

US20040029323A1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20040029323A1
公开(公告)日：2004-02-12
申请号：US10363065
申请日：2003-08-13
发明人： Akihiro Shimizu , Nagatoshi Ooki , Yusuke Nonaka , Katsuhiko Ichinose
IPC分类号： H01L021/335
CPC分类号： H01L29/7845 , H01L21/0217 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823864 , H01L21/84 , H01L27/092 , H01L27/0922 , H01L29/665 , H01L29/6659 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.
摘要翻译：半导体器件具有n沟道导电型场效应晶体管，其具有形成在半导体衬底的一个主表面上的第一区域中的沟道形成区域和具有形成在第二区域中的沟道形成区域的ap沟道导电型场效应晶体管，半导体衬底的主表面，该第二区域与第一区域不同。在n沟道导电型场效应晶体管的沟道形成区域中产生的内应力与在p沟道导电型场效应晶体管的沟道形成区域中产生的内应力不同。在n沟道导电型场效应晶体管的沟道形成区域中产生的内应力是拉伸应力，而在p沟道导电型场效应晶体管的沟道形成区域中产生的内应力是压应力。

20. 发明申请

US20020110986A1 Dual doped gates 失效
标题翻译：双掺杂栅极
公开(公告)号：US20020110986A1
公开(公告)日：2002-08-15
申请号：US09782743
申请日：2001-02-13
申请人： Micron Technology, Inc
发明人： Howard E. Rhodes
IPC分类号： H01L021/335 , H01L021/8232 , H01L021/338 , H01L021/8238 , H01L021/336
CPC分类号： H01L21/823892 , H01L21/2652 , H01L21/823842
摘要： A method of forming an integrated circuit dual gate structure using only one mask is disclosed. In one embodiment, a substrate is prepared for the fabrication of a dual gate structure, a first gate structure having an NWELL is formed without using a mask, and a second gate structure having a PWELL is formed using only one mask. In an alternate embodiment, a substrate is prepared for the fabrication of a dual gate structure, a first gate structure having a PWELL is formed without using a mask, and a second gate structure having an NWELL is formed using only one mask.
摘要翻译：公开了仅使用一个掩模形成集成电路双栅极结构的方法。在一个实施例中，制备用于制造双栅极结构的衬底，在不使用掩模的情况下形成具有NWELL的第一栅极结构，并且仅使用一个掩模形成具有PWELL的第二栅极结构。在替代实施例中，准备用于制造双栅极结构的衬底，在不使用掩模的情况下形成具有PWELL的第一栅极结构，并且仅使用一个掩模形成具有NWELL的第二栅极结构。

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