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11. 发明授权

US08243865B2 Data processing apparatus 有权
标题翻译：数据处理装置
公开(公告)号：US08243865B2
公开(公告)日：2012-08-14
申请号：US11763663
申请日：2007-06-15
申请人： Nobunari Tsukamoto , Hidetoshi Ema
发明人： Nobunari Tsukamoto , Hidetoshi Ema
IPC分类号： H04L7/00
CPC分类号： H03M7/3048
摘要： A disclosed data processing apparatus includes: a binarization unit binarizing input data based on a threshold voltage; a capture unit capturing data from a binary output binarized by the binarization unit; a duty cycle detection unit detecting a duty cycle of the binary output; and a control unit controlling a level of the input data based on the duty cycle detected by the duty cycle detection unit.
摘要翻译：公开的数据处理装置包括：二值化单元，基于阈值电压二值化输入数据; 捕获单元，从由二值化单元二值化的二进制输出中获取数据; 占空比检测单元，检测二进制输出的占空比; 以及控制单元，其基于由占空比检测单元检测到的占空比来控制输入数据的电平。

12. 发明授权

US4630007A Delta modulated signal sampling rate converter using digital means 失效
标题翻译： Delta调制信号采样率转换器采用数字方式
公开(公告)号：US4630007A
公开(公告)日：1986-12-16
申请号：US742883
申请日：1985-06-10
申请人： Roger Lagadec
发明人： Roger Lagadec
IPC分类号： H03M7/32 , H03M7/00 , H04B14/06 , H03C3/00
CPC分类号： H03M7/3048 , H04B14/062
摘要： In the conversion of a first delta modulated signal with a first bit rate into a second delta modulated signal with a second bit rate, a first and second digital signal derived respectively from the first and second delta modulated signals are compared together in an adding circuit (58) followed by an integration circuit (55). In this way an analog intermediary signal can be avoided and the circuit complexity is small.
摘要翻译：在将具有第一比特率的第一增量调制信号转换成具有第二比特率的第二增量调制信号时，分别从第一和第二增量调制信号导出的第一和第二数字信号在加法电路 58），随后是积分电路（55）。以这种方式，可以避免模拟中介信号，并且电路复杂度小。

13. 发明授权

USB295674I5 失效
公开(公告)号：USB295674I5
公开(公告)日：1975-01-28
申请号：US29567472
申请日：1972-10-06
IPC分类号： H03M7/00 , H04J3/00 , H04J3/06 , H04L5/22 , H04L25/05
CPC分类号： H03M7/3048 , H04J3/00 , H04J3/06 , H04J3/062 , H04L25/05

14. 发明授权

US3772678A Converter from pulse code modulation to delta modulation 失效
标题翻译：脉冲代码调制转换为DELTA调制
公开(公告)号：US3772678A
公开(公告)日：1973-11-13
申请号：US3772678D
申请日：1972-05-22
申请人： UNIV SHERBROOKE
发明人： DESCHENES P , VILLERET M
IPC分类号： H03M7/00 , H03K11/00 , H03K13/24
CPC分类号： H03M7/3048
摘要： The system for the conversion of a PCM modulation signal into a Delta M modulation signal comprises: first register means for storing an input signal consisting of m binary digits representing the value x of the quantized signal at the end of a regular PCM modulation sampling period Ti; a ''''digital integrator'''' for storing the value e of the quantized signal at the end of sampling period Ti 1; a comparator connected to the first register means and to the digital integrator for comparing the value of the quantized signal x stored in the first register means with the value of the quantized signal e stored in the digital integrator and for generating a positive binary output signal Z if x is larger than e and a negative output signal Z if x is smaller than e; and second register means connected to the comparator for storing said output signal which is representative of the Delta M modulation signal.
摘要翻译：用于将PCM调制信号转换为DELTA M调制信号的系统包括：第一寄存器装置，用于存储在常规PCM调制采样周期Ti结束时由表示量化信号的值x的m个二进制数组成的输入信号 ; 用于在采样周期Ti-1结束时存储量化信号的值e的“数字积分器”; 连接到第一寄存器装置的比较器和数字积分器，用于将存储在第一寄存器装置中的量化信号x的值与存储在数字积分器中的量化信号e的值进行比较，并产生正二进制输出信号Z 如果x大于e，负输出信号Z如果x小于e; 以及连接到比较器的第二寄存器装置，用于存储表示DELTA M调制信号的所述输出信号。

15. 发明授权

US3737780A Digital communication system employing unity bit per sampling coding method 失效
标题翻译：数字通信系统采用采样编码方式的UNITY位
公开(公告)号：US3737780A
公开(公告)日：1973-06-05
申请号：US3737780D
申请日：1971-05-04
申请人： NIPPON ELECTRIC CO
发明人： TOMOZAWA A
IPC分类号： H03M7/32 , H03M7/00 , H04B1/00
CPC分类号： H03M7/3048
摘要： A digital communication system reduces the transmission speed required to propagate signals resulting from a unity bit per sample coding process, e.g., delta modulation or delta-sigma modulation. The modulation wave pulses produced during cyclically recurring code converting intervals are counted and the count state transmitted rather than the modulation signal per se, thereby reducing the signal rate impressed on the communication channel. An inverse procedure is employed for signal recovery.
摘要翻译：数字通信系统降低传播由每个样本编码处理的单位比特产生的信号所需的传输速度，例如增量调制或Δ-Σ调制。在循环重复码转换间隔期间产生的调制波脉冲被计数，并且发送计数状态而不是调制信号本身，从而降低了施加在通信信道上的信号速率。信号恢复采用逆过程。

16. 发明授权

US09589591B2 Signal processing device, signal processing method, and computer program 有权
标题翻译：信号处理装置，信号处理方法和计算机程序
公开(公告)号：US09589591B2
公开(公告)日：2017-03-07
申请号：US14534592
申请日：2014-11-06
申请人： SONY CORPORATION
发明人： Yuuki Matsumura , Shiro Suzuki
IPC分类号： G11B20/10 , H03M7/30 , H03M3/00 , G11B20/00
CPC分类号： G11B20/10037 , G11B20/10027 , G11B2020/00065 , H03M3/30 , H03M7/3004 , H03M7/3013 , H03M7/3031 , H03M7/3044 , H03M7/3048
摘要： There is provided a signal processing device including a signal coincidence detection portion which detects samples, in which values based on a number of times of appearance of bits coincide with each other over a plurality of samples within a pre-set period, between a first modulated signal obtained by delaying an input signal obtained by ΣΔ modulation and a second modulated signal obtained by subjecting the input signal to the ΣΔ modulation again, a signal changeover portion which switches between the first modulated signal and the second modulated signal for outputting, and a switching control portion which controls the switching between the first modulated signal and the second modulated signal by the signal changeover portion in the samples in which the values based on the number of times of the appearance coincide with each other obtained by the signal coincidence detection portion.
摘要翻译：提供了一种信号处理装置，包括信号一致检测部分，其检测样本，其中基于比特出现次数的值在预设时段内在多个样本之间彼此重合的值在第一调制通过延迟通过ΣΔ调制获得的输入信号而获得的信号和通过再次对输入信号进行ΣΔ调制而获得的第二调制信号，在第一调制信号和第二调制信号之间切换以输出的信号切换部分，以及切换控制部分，其通过由信号重合检测部分获得的基于出现次数彼此重合的值的样本中的信号切换部分来控制第一调制信号和第二调制信号之间的切换。

17. 发明申请

US20070297548A1 DATA PROCESSING APPARATUS 有权
标题翻译：数据处理设备
公开(公告)号：US20070297548A1
公开(公告)日：2007-12-27
申请号：US11763663
申请日：2007-06-15
申请人： Nobunari Tsukamoto , Hidetoshi Ema
发明人： Nobunari Tsukamoto , Hidetoshi Ema
IPC分类号： H04L7/00
CPC分类号： H03M7/3048
摘要： A disclosed data processing apparatus includes: a binarization unit binarizing input data based on a threshold voltage; a capture unit capturing data from a binary output binarized by the binarization unit; a duty cycle detection unit detecting a duty cycle of the binary output; and a control unit controlling a level of the input data based on the duty cycle detected by the duty cycle detection unit.
摘要翻译：公开的数据处理装置包括：二值化单元，基于阈值电压二值化输入数据; 捕获单元，从由二值化单元二值化的二进制输出中获取数据; 占空比检测单元，检测二进制输出的占空比; 以及控制单元，其基于由占空比检测单元检测到的占空比来控制输入数据的电平。

18. 发明授权

US4433423A High quality delta modulator 失效
标题翻译：高品质三角洲调制器
公开(公告)号：US4433423A
公开(公告)日：1984-02-21
申请号：US344131
申请日：1982-01-29
申请人： Scott M. Golding
发明人： Scott M. Golding
IPC分类号： H03M3/02 , G11B3/00 , G11B7/00 , G11B7/004 , G11B20/10 , H03M7/00 , H04B14/06 , H03K13/22 , H04B12/04
CPC分类号： H03M7/3048
摘要： Method and apparatus for generating a series of delta modulation data signals corresponding to a predetermined analog waveform wherein an error determination comparison is made on a sequentially generated series of potential delta modulation data signals to determine the optimum pattern of delta modulation bits. The method can be performed in iterative fashion for each delta modulation bit generated.
摘要翻译：用于产生对应于预定模拟波形的一系列增量调制数据信号的方法和装置，其中对顺序产生的一系列电位增量调制数据信号进行误差确定比较，以确定增量调制比特的最佳模式。可以以生成的每个增量调制位的迭代方式执行该方法。

19. 发明授权

US3962636A Device for converting an incoming analog signal into an outgoing PCM signal 失效
标题翻译：用于将输入模拟信号转换成输出PCM信号的装置
公开(公告)号：US3962636A
公开(公告)日：1976-06-08
申请号：US529800
申请日：1974-12-05
申请人： Gunnar Erik William Sparrendahl
发明人： Gunnar Erik William Sparrendahl
IPC分类号： H03M7/00 , H04B14/06 , H04J3/02 , H03K13/22
CPC分类号： H03M7/3048 , H04B14/062 , H04J3/02
摘要： The invention relates to a device for converting an incoming analog signal into an outgoing PCM signal, comprising a .DELTA. M-encoder in which a comparator circuit has a first and a second analog input of which the first analog input is arranged to be fed with the incoming signal and a digital output arranged to supply a delta signal with a clock frequency considerably higher than the upper limit frequency of the incoming signal and in which a feedback filter for the delta signal is connected between the digital output and the second analog input of the comparator circuit, and a digital .DELTA. M-PCM converter in which a digital filter is connected to the digital output of the comparator circuit in the .DELTA. M-encoder and is arranged to generate an average signal related to the delta signal and a PCM word generator is connected in cascade with the digital filter and is arranged to generate the outgoing PCM signal with a sampling frequency considerably lower than the clock frequency.
摘要翻译：本发明涉及一种用于将输入的模拟信号转换成输出PCM信号的装置，包括一个DELTA M编码器，其中比较器电路具有第一和第二模拟输入，第一模拟输入和第二模拟输入被配置为馈送输入信号和数字输出，其布置成提供具有显着高于输入信号的上限频率的时钟频率的增量信号，并且其中用于增量信号的反馈滤波器连接在数字输出和第二模拟输入之间比较器电路和数字DELTA M-PCM转换器，其中数字滤波器连接到DELTA M编码器中的比较器电路的数字输出，并且被布置为产生与Δ信号相关的平均信号和PCM字生成器与数字滤波器级联连接，并且被布置成产生具有比时钟频率显着更低的采样频率的输出PCM信号。

20. 发明授权

US3707712A Converter from delta modulation to pulse code modulation 失效
标题翻译：从DELTA调制转换为脉冲代码调制
公开(公告)号：US3707712A
公开(公告)日：1972-12-26
申请号：US3707712D
申请日：1970-06-10
申请人： UNIV SHERBROOKE
发明人： DESCHENES PIERRE A , VILLERET MICHEL
IPC分类号： H03M7/00 , H03K11/00 , H03K13/00 , H03K13/24
CPC分类号： H03M7/3048
摘要： A system for the conversion of a delta modulation ( Delta M) signal into a pulse code modulation (PCM) signal and vice versa. The system for the conversion of a Delta M modulation signal into a PCM modulation signal comprises: register means for storing an input signal consisting of n binary digits generated by a Delta M modulator during a time period corresponding to a normal PCM modulation sampling period Ti, each binary digit representing a positive or negative Delta M modulation quantization step of a quantized signal; means for effecting the algebraic sum of the positive and negative quantization steps to obtain the increase or decrease of the quantized signal during the sampling period; means for multiplying the algebraic sum by a constant K representing the ratio of the value of a Delta M modulation quantization step over the value of a PCM modulation quantization step to obtain a binary signal representing the increase or decrease of the quantized signal in pulse code modulation quantization steps; and means for adding the binary signal obtained by the above multiplication to the binary signal obtained during the sampling period Ti 1 to obtain a binary output signal corresponding to the required pulse code modulation signal.
摘要翻译：用于将增量调制（DELTA M）信号转换为脉冲编码调制（PCM）信号的系统，反之亦然。用于将DELTA M调制信号转换成PCM调制信号的系统包括：寄存器装置，用于在对应于正常PCM调制采样周期Ti的时间段内存储由DELTA M调制器产生的n个二进制数字组成的输入信号，每个二进制数字表示量化信号的正或负DELTA M调制量化步骤; 用于实现正和负量化步长的代数和以获得在采样周期期间量化信号的增加或减少的装置; 用于将代数和乘以表示DELTA M调制量化步长的值与PCM调制量化步长的值的比率的常数K以获得表示脉冲编码调制中量化信号的增加或减小的二进制信号的装置量化步骤; 以及用于将通过上述乘法获得的二进制信号与在采样周期Ti-1期间获得的二进制信号相加以获得与所需脉冲编码调制信号相对应的二进制输出信号的装置。

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