会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 15. 发明申请
    • DECODING OF SERIAL CONCATENATED CODES USING ERASURE PATTERNS
    • 使用擦除图案解码串行编码
    • US20100146372A1
    • 2010-06-10
    • US12520214
    • 2007-12-14
    • Martin TomlinsonMarcel Ambroze
    • Martin TomlinsonMarcel Ambroze
    • H03M13/45G06F11/10
    • H03M13/293H03M13/2915
    • A method of processing a received concatenated code codeword is disclosed, the concatenated code codeword comprising a plurality of inner code codewords and one or more outer code codewords, each inner code codeword comprising symbols, from each outer code codeword comprising one or more information symbols and one or more parity symbols, the parity symbols in each outer code codeword corresponding to the parity check equations of the outer code. The method comprises (i) decoding the received concatenated code codeword; (ii) erasing a subset of the received inner code codewords; and (iii) determining a replacement inner code codeword to replace each of the erased inner code codewords to provide a candidate concatenated code codeword. A preferred method further comprises (iv) erasing a further, different subset of the received inner code codewords; (v) determining further replacement inner code codewords to replace each of the thus erased inner code codewords to provide a further candidate concatenated code codeword; and (vi) determining the candidate concatenated code codeword having the highest correlation with the received vector of the decoded concatenated code codeword. A system for performing the method is also disclosed.
    • 公开了一种处理接收的级联码字的方法,包括多个内码码字和一个或多个外码码字的连接码码字,每个内码码字包括符号,每个外码码字包括一个或多个信息符号, 一个或多个奇偶校验符号,对应于外部码的​​奇偶校验方程的每个外码码字中的奇偶校验符号。 该方法包括:(i)解码所接收的级联码字; (ii)擦除所接收的内码码字的子集; 和(iii)确定替代内码码字以替换每个被擦除的内码码字以提供候选连接码码字。 优选方法还包括(iv)擦除所接收的内码码字的另一不同子集; (v)确定进一步的替换内码码字以替换由此被擦除的内码码字中的每一者以提供另外的候选连接码码字; 和(vi)确定与解码的级联码字字的接收向量具有最高相关性的候选级联码字。 还公开了一种用于执行该方法的系统。
    • 16. 发明授权
    • Semiconductor memory device having error correction function
    • 半导体存储器件具有纠错功能
    • US07656322B2
    • 2010-02-02
    • US12175473
    • 2008-07-18
    • Daisuke Oda
    • Daisuke Oda
    • H03M13/00
    • H03M13/27H03M13/1165H03M13/15H03M13/152H03M13/19H03M13/2906H03M13/2909H03M13/2915
    • A semiconductor memory device configured such that the time required for its access test can be reduced comprising a memory cell array, a row decoder, a column decoder, an error correction circuit, and an output circuit. The error correction circuit performs error correction on a code word read through the bit lines selected by the column decoder from ones of memory cells located at places at which the word line selected by the row decoder and the selected bit lines cross over, thereby detecting an error position in the code word to generate error detection data indicating the error position and corrects the information bit in the detected error position to generate error corrected data. The output circuit relays to the outside the error corrected data when a normal operation mode has been designated and the error detection data when a test operation mode has been designated.
    • 一种半导体存储器件,被配置为使得可以减少其访问测试所需的时间,包括存储单元阵列,行解码器,列解码器,纠错电路和输出电路。 错误校正电路对由列解码器选择的位线读取的代码字进行错误校正,位于由行解码器选择的字线和所选位线交叉的位置处的存储单元之间,从而检测 代码字中的错误位置,以产生指示错误位置的错误检测数据,并校正检测到的错误位置中的信息位以产生纠错数据。 当指定了正常操作模式时,输出电路向外部中断纠错数据,并且当指定了测试操作模式时,该错误检测数据。