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11. 发明授权

US09660655B2 Ultra low phase noise frequency synthesizer 有权
公开(公告)号：US09660655B2
公开(公告)日：2017-05-23
申请号：US15379915
申请日：2016-12-15
申请人： Yekutiel Josefsberg , Tal I. Lavian
发明人： Yekutiel Josefsberg , Tal I. Lavian
IPC分类号： H03L7/08 , H03L7/07 , H03L7/20 , H03L1/02
CPC分类号： H03L7/085 , H03L1/028 , H03L7/07 , H03L7/099 , H03L7/113 , H03L7/185 , H03L7/20 , H03L7/23 , H03L7/24
摘要： A system for providing ultra low phase noise frequency synthesizers using Fractional-N PLL (Phase Lock Loop), Sampling Reference PLL and DDS (Direct Digital Synthesizer). Modern day advanced communication systems comprise frequency synthesizers that provide a frequency output signal to other parts of the transmitter and receiver so as to enable the system to operate at the set frequency band. The performance of the frequency synthesizer determines the performance of the communication link. Current days advanced communication systems comprises single loop Frequency synthesizers which are not completely able to provide lower phase deviations for errors (For 256 QAM the practical phase deviation for no errors is 0.4-0.5°) which would enable users to receive high data rate. This proposed system overcomes deficiencies of current generation state of the art communication systems by providing much lower level of phase deviation error which would result in much higher modulation schemes and high data rate.

12. 发明申请

US20160315628A1 Frequency Generator with Two Voltage Controlled Oscillators 审中-公开
标题翻译：带两个压控振荡器的频率发生器
公开(公告)号：US20160315628A1
公开(公告)日：2016-10-27
申请号：US15132678
申请日：2016-04-19
申请人： Endress + Hauser GmbH + Co. KG
发明人： Winfried Mayer , Martin Hitzler , Christian Waldschmidt
IPC分类号： H03L7/23 , G01S13/32 , H03L7/099 , H03L7/185 , H03L7/093 , G01F23/284 , H03L7/197
CPC分类号： H03L7/23 , G01F23/284 , G01S7/35 , G01S13/345 , G01S13/88 , H03L7/099 , H03L7/1976 , H03L2207/06
摘要： Described is a frequency generator for producing a frequency ramp. The frequency generator includes a first voltage controlled oscillator, which has a plurality of switchable sub-bands and is designed to produce a first frequency signal, wherein a switching from one sub-band to a neighboring sub-band occurs at predetermined first switching locations, as well as a second voltage controlled oscillator, which has a plurality of switchable sub-bands and is designed to produce a second frequency signal. A switching from one sub-band to a neighboring sub-band occurs at predetermined second switching locations. The sub-bands of the second voltage controlled oscillator are arranged offset in frequency relative to the sub-bands of the first voltage controlled oscillator. The frequency generator is designed to switch either the first frequency signal or the second frequency signal through to the output of the electronic switch element, and to switch the electronic switch element such that during the producing of the frequency ramp alternately either the first frequency signal or the second frequency signal is switched through to the output of the electronic switch element, wherein, in each case, when at one of the voltage controlled oscillators the switching between two neighboring sub-bands is occurring, the frequency signal produced by the respectively other voltage controlled oscillator is switched through to the output of the electronic switch element.
摘要翻译：描述了用于产生频率斜坡的频率发生器。频率发生器包括第一压控振荡器，其具有多个可切换子带，并被设计为产生第一频率信号，其中在预定的第一切换位置发生从一个子带到相邻子带的切换，以及第二压控振荡器，其具有多个可切换子带并被设计为产生第二频率信号。在预定的第二切换位置发生从一个子带到相邻子带的切换。第二压控振荡器的子带被布置为相对于第一压控振荡器的子带的频率偏移。频率发生器被设计成将第一频率信号或第二频率信号切换到电子开关元件的输出，并且切换电子开关元件，使得在频率斜坡的交替产生期间，第一频率信号或第二频率信号被切换到电子开关元件的输出，其中，在每种情况下，当在一个压控振荡器处于两个相邻子带之间的切换时，发生由相应的其它电压产生的频率信号受控振荡器切换到电子开关元件的输出端。

13. 发明申请

US20160285468A1 VOLTAGE CONTROLLED OSCILLATOR RUNAWAY PREVENTION 有权
公开(公告)号：US20160285468A1
公开(公告)日：2016-09-29
申请号：US14733993
申请日：2015-06-09
申请人： International Business Machines Corporation
发明人： David M. Friend , James D. Strom , Alan P. Wagstaff
IPC分类号： H03L7/14
CPC分类号： H03L7/085 , H03B5/06 , H03K23/42 , H03L3/00 , H03L7/07 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H03L7/22 , H03L7/23
摘要： A feedback module for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit can include a first, a second, and a third input to receive a first output signal from a PLL circuit, a reference signal, and a first control signal. The feedback module may also include a feedback circuit to generate a second control signal, the second control signal being coupled to an input of the PLL circuit, wherein the feedback circuit generates the second control signal by comparing a number of cycles of the first output signal to a first threshold, and a number of cycles of the reference signal to a second threshold.

14. 发明授权

US09325927B2 Method of operating a multi-stream reception scheme 有权
标题翻译：操作多流接收方案的方法
公开(公告)号：US09325927B2
公开(公告)日：2016-04-26
申请号：US12865991
申请日：2009-02-03
申请人： Yann Le Guillou
发明人： Yann Le Guillou
IPC分类号： H04B1/06 , H04N5/455 , H03L7/197 , H03L7/23 , H04N21/61 , H04N21/426
CPC分类号： H04N5/455 , H03L7/1976 , H03L7/23 , H04N21/4263 , H04N21/42676 , H04N21/6118
摘要： A method of operating a multi-stream reception scheme, such as DOCSIS (Data Over Cable Service Interface Specifications), comprising at least two receivers (10, 12, 14) having respective voltage controlled oscillators (16), the method including monitoring a change in local oscillator frequency in a selected one of the at least two streams and, if the frequency distance between the local oscillator frequencies is below a value likely to cause pulling or coupling between the voltage controlled oscillators of the at least two receivers, resetting the frequency planning of the selected one of the at least two streams to maximize the frequency distance of the voltage controlled oscillator of the selected stream with the voltage controlled oscillators of the or the other streams.
摘要翻译：一种操作诸如DOCSIS（Data Over Cable Service Interface Specifications）的多流接收方案的方法，包括至少两个具有各自的压控振荡器（16）的接收器（10,12,14），该方法包括监视变化在所述至少两个流中所选择的一个中的本地振荡器频率中，并且如果所述本地振荡器频率之间的频率距离低于可能导致所述至少两个接收机的压控振荡器之间的拉或耦合的值，则重置所述频率规划所述至少两个流中所选择的一个流，以使所选择的流的压控振荡器的频率距离与所述或其它流的压控振荡器最大化。

15. 发明申请

US20160105188A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160105188A1
公开(公告)日：2016-04-14
申请号：US14837731
申请日：2015-08-27
申请人： JONG-PIL CHO , YOUNG-JOO LEE
发明人： JONG-PIL CHO , YOUNG-JOO LEE
IPC分类号： H03L7/087 , H04L7/00 , H04B5/00 , H04L7/033 , H03L7/089 , H03L7/099
CPC分类号： H03L7/087 , H03L7/0805 , H03L7/0814 , H03L7/18 , H03L7/23 , H04B5/0025 , H04B5/0031 , H04B5/0056 , H04L7/0008
摘要： A semiconductor device including a PLL providing candidate clocks of different phases in response to a first clock received from a reader via an antenna, a phase difference detector detecting a phase difference between the first clock and a clock from the candidate clocks, a phase difference controller that selects another clock from the candidate clocks, and a driver that provides transmission data synchronously with the another clock to the reader.
摘要翻译：一种半导体器件，包括响应于从读取器经由天线接收的第一时钟，提供不同相位的候选时钟的PLL;相位差检测器，检测来自候选时钟的第一时钟和时钟之间的相位差;相位差控制器从候选时钟中选择另一个时钟，以及向读取器提供与另一时钟同步的传输数据的驱动器。

16. 发明申请

US20160072440A1 Digital Calibration for Multiphase Oscillators 有权
标题翻译：多相振荡器的数字校准
公开(公告)号：US20160072440A1
公开(公告)日：2016-03-10
申请号：US14858965
申请日：2015-09-18
申请人： Rambus Inc.
发明人： Mohammad Hekmat , Reza Navid
IPC分类号： H03B27/00 , H03L7/099
CPC分类号： H03B27/00 , H03L7/06 , H03L7/099 , H03L7/23
摘要： A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.
摘要翻译：锁相环电路包括具有多个耦合振荡器的多相振荡器。校准模块在校准过程中检测锁相环电路中的不同振荡器的频率特性之间的不匹配。校准模块然后校准各种振荡器以补偿检测到的失配。一旦校准，尽管不同振荡器之间的频率特性不匹配，锁相环电路可以很少或没有性能下降。

17. 发明申请

US20160043728A1 RF CIRCUIT 有权
标题翻译：射频电路
公开(公告)号：US20160043728A1
公开(公告)日：2016-02-11
申请号：US14821481
申请日：2015-08-07
申请人： NXP B.V.
发明人： Jean-Robert Tourret
IPC分类号： H03L7/18 , H05B6/00
CPC分类号： H03L7/235 , H03L7/07 , H03L7/099 , H03L7/18 , H03L7/22 , H03L7/23 , H05B6/00
摘要： An RF circuit for providing phase coherent signals, an RF heating apparatus comprising the RF circuit and a method for providing phase coherent signals in an RF circuit. The RF circuit has a first frequency synthesiser including a fractional-N phase locked loop and a second frequency synthesiser including an integer-N phase locked loop. An output of the first frequency synthesiser is connected to a phase frequency detector of the integer-N phase locked loop of the second frequency synthesiser via a synchronisation signal divider for distributing a synchronisation signal from the first frequency synthesiser to the second frequency synthesiser. The integer-N phase locked loop of the second frequency synthesiser comprises a frequency divider of the same modulus as the synchronisation signal divider.
摘要翻译：一种用于提供相位相干信号的RF电路，包括RF电路的RF加热装置和用于在RF电路中提供相位相干信号的方法。 RF电路具有包括N分相锁相环的第一频率合成器和包括整数N个锁相环的第二频率合成器。第一频率合成器的输出经由用于将来自第一频率合成器的同步信号分配给第二频率合成器的同步信号分频器连接到第二频率合成器的整数N锁相环的相位频率检测器。第二频率合成器的整数N锁相环包括与同步信号分频器相同模数的分频器。

18. 发明授权

US09225508B1 Low-noise flexible frequency clock generation from two fixed-frequency references 有权
公开(公告)号：US09225508B1
公开(公告)日：2015-12-29
申请号：US14791329
申请日：2015-07-03
申请人： PMC-SIERRA US, INC.
发明人： William Michael Lye , Hormoz Djahanshahi
IPC分类号： H03L7/18 , H03L7/093 , H04L7/033 , H04L7/00
CPC分类号： H03L7/07 , H03L7/087 , H03L7/099 , H03L7/185 , H03L7/1974 , H03L7/1976 , H03L7/23 , H03L7/235 , H03L2207/12 , H04L7/0025 , H04L7/0331 , H04L7/0332
摘要： A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.

19. 发明授权

US09215676B2 Base station clock apparatus, base station system and method for clock synchronization 有权
标题翻译：基站时钟装置，基站系统及时钟同步方法
公开(公告)号：US09215676B2
公开(公告)日：2015-12-15
申请号：US13946184
申请日：2013-07-19
申请人： HUAWEI TECHNOLOGIES CO., LTD.
发明人： Weidong Yu , Yuhong Chu
IPC分类号： H04W56/00 , H04W88/08 , H04L7/033 , H03L7/23
CPC分类号： H04W56/00 , H03L7/23 , H04J3/0688 , H04L7/0337 , H04W56/0015 , H04W56/0035 , H04W88/08
摘要： A base station clock apparatus, a base station system, and a method for clock synchronization are provided in embodiments of the present invention. The base station clock apparatus includes: a first-standard clock module based on a first standard, configured to generate a first frequency synchronization clock signal, a first phase synchronization signal, and a first system clock signal according to a first external clock signal, where the first system clock signal includes the first frequency synchronization clock signal and the first phase synchronization signal; a second-standard clock module based on a second standard that is different from the first standard, configured to receive the first frequency synchronization clock signal and the first phase synchronization signal from the first-standard clock module, and generate a second system clock signal, where the second system clock signal includes the first frequency synchronization clock signal and the first phase synchronization signal.
摘要翻译：在本发明的实施例中提供了基站时钟装置，基站系统和时钟同步方法。基站时钟装置包括：基于第一标准的第一标准时钟模块，被配置为根据第一外部时钟信号产生第一频率同步时钟信号，第一相位同步信号和第一系统时钟信号，其中第一系统时钟信号包括第一频率同步时钟信号和第一相位同步信号; 基于与第一标准不同的第二标准的第二标准时钟模块，被配置为从第一标准时钟模块接收第一频率同步时钟信号和第一相位同步信号，并产生第二系统时钟信号，其中第二系统时钟信号包括第一频率同步时钟信号和第一相位同步信号。

20. 发明申请

US20150303873A1 SPIN-TRANSFER TORQUE TYPE INJECTION LOCKING OSCILLATOR AND DESIGN METHOD THEREOF 有权
标题翻译：转子扭矩型注射锁止振荡器及其设计方法
公开(公告)号：US20150303873A1
公开(公告)日：2015-10-22
申请号：US14440983
申请日：2013-10-16
申请人： KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
发明人： ChulSoon Park , SeongJun Cho
IPC分类号： H03B15/00 , H01L43/12 , G06F17/50
CPC分类号： H03B15/006 , B82Y25/00 , G01R33/093 , G01R33/098 , G01R33/1284 , G06F17/5068 , H01F10/329 , H01L43/12 , H03B27/00 , H03L7/23 , H03L7/24
摘要： The present invention provides a spin-transfer torque type injection locking oscillator which improves both power and noise performance by using pair of spin-transfer torque devices. One is optimized for high power and the other is optimized for low noise characteristics. The output signal of the low noise spin-transfer torque device is injected into the high output power spin-transfer torque for phase locking. The present invention has several advantages such as the miniaturization, the high quality and low cost, and the mass production of integrated chips by the nanoscale.
摘要翻译：本发明提供了一种通过使用一对自旋转移转矩装置来提高功率和噪声性能的自旋转移转矩型注入锁定振荡器。一个针对高功率进行了优化，另一个针对低噪声特性进行了优化。低噪声自旋转移转矩装置的输出信号被注入到用于锁相的高输出功率的自旋转移转矩中。本发明具有微型化，高品质，低成本，纳米级集成芯片的大量生产等优点。

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