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11. 发明申请

US20180102783A1 Fractional PLLs with Low Correlation 有权
公开(公告)号：US20180102783A1
公开(公告)日：2018-04-12
申请号：US15556335
申请日：2015-03-20
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： Henrik Sjöland , Staffan Ek , Tony Påhlsson
IPC分类号： H03L7/197 , H03L7/185 , H04B7/06 , H03L7/08
CPC分类号： H03L7/1976 , H03L7/0802 , H03L7/185 , H03L7/23 , H03L2207/12 , H04B7/0617
摘要： The programmable frequency control system presented herein provides frequency programmability and phase noise reduction for signals generated by a plurality of frequency programmable phase-locked loops (PLLs). In general, a modulated data stream input to each of the plurality of PLLs controls the frequency of the signal output by the PLLs. The solution presented herein reduces the phase noise by introducing a time shift to the modulated data stream applied to at least some of the PLLs so that at least some of the PLLs receive time-shifted versions of the modulated data stream relative to other PLLs. In so doing, the solution presented herein decorrelates the quantization noise generated by the plurality of frequency programmable PLLs.

12. 发明申请

US20180091158A1 CIRCUIT DEVICE, PHYSICAL QUANTITY MEASUREMENT APPARATUS, ELECTRONIC APPARATUS, AND VEHICLE 审中-公开
公开(公告)号：US20180091158A1
公开(公告)日：2018-03-29
申请号：US15715458
申请日：2017-09-26
申请人： Seiko Epson Corporation
发明人： Yasuhiro SUDO , Katsuhiko MAKI , Hideo HANEDA , Akio TSUTSUMI , Takashi KURASHINA
IPC分类号： H03L7/087 , G04F10/00
CPC分类号： H03L7/087 , G04F10/005 , H03L7/18 , H03L7/23
摘要： A circuit device includes: a time-to-digital conversion circuit to which a first clock signal with a first clock frequency and a second clock signal with a second clock frequency different from the first clock frequency are input and that converts a time difference in transition timings of first and second signals into a digital value; and a synchronization circuit that synchronizes phases of the first and second clock signals. The time-to-digital conversion circuit calculates the digital value corresponding to the time difference by transitioning a signal level of the first signal based on the first clock signal after a phase synchronization timing of the first and second clock signals and compares the phase of the second clock signal to a phase of the second signal having a signal level is transitioned to correspond to the first signal.

13. 发明申请

US20180006655A1 DEVICE AND METHOD TO CALIBRATE FREQUENCY 审中-公开
公开(公告)号：US20180006655A1
公开(公告)日：2018-01-04
申请号：US15610112
申请日：2017-05-31
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Seong Joong KIM , Sang Joon KIM , Jong Pal KIM
IPC分类号： H03L7/085 , H03L7/099 , H03L1/02
CPC分类号： H03L1/02 , H03J7/00 , H03L7/23
摘要： A frequency calibration device includes an input signal generator configured to generate an input signal based on an oscillation signal and an external signal, an envelope detector configured to detect an envelope signal corresponding to the input signal, and a frequency tuner configured to tune an oscillation frequency of the oscillation signal based on an envelope frequency corresponding to the envelope signal.

14. 发明申请

US20170264425A1 HIGH ORDER HYBRID PHASE LOCKED LOOP WITH DIGITAL SCHEME FOR JITTER SUPPRESSION 有权
公开(公告)号：US20170264425A1
公开(公告)日：2017-09-14
申请号：US15064975
申请日：2016-03-09
申请人： Sadok Aouini , Naim Ben-Hamida , Mahdi Parvizi
发明人： Sadok Aouini , Naim Ben-Hamida , Mahdi Parvizi
IPC分类号： H04L7/033
CPC分类号： H04L7/0331 , H03L7/06 , H03L7/07 , H03L7/0802 , H03L7/0805 , H03L7/081 , H03L7/0814 , H03L7/085 , H03L7/087 , H03L7/093 , H03L7/099 , H03L7/0992 , H03L7/18 , H03L7/1806 , H03L7/193 , H03L7/1974 , H03L7/1976 , H03L7/23 , H03L7/235 , H03L2207/06 , H03L2207/50
摘要： A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.

15. 发明授权

US09660655B2 Ultra low phase noise frequency synthesizer 有权
公开(公告)号：US09660655B2
公开(公告)日：2017-05-23
申请号：US15379915
申请日：2016-12-15
申请人： Yekutiel Josefsberg , Tal I. Lavian
发明人： Yekutiel Josefsberg , Tal I. Lavian
IPC分类号： H03L7/08 , H03L7/07 , H03L7/20 , H03L1/02
CPC分类号： H03L7/085 , H03L1/028 , H03L7/07 , H03L7/099 , H03L7/113 , H03L7/185 , H03L7/20 , H03L7/23 , H03L7/24
摘要： A system for providing ultra low phase noise frequency synthesizers using Fractional-N PLL (Phase Lock Loop), Sampling Reference PLL and DDS (Direct Digital Synthesizer). Modern day advanced communication systems comprise frequency synthesizers that provide a frequency output signal to other parts of the transmitter and receiver so as to enable the system to operate at the set frequency band. The performance of the frequency synthesizer determines the performance of the communication link. Current days advanced communication systems comprises single loop Frequency synthesizers which are not completely able to provide lower phase deviations for errors (For 256 QAM the practical phase deviation for no errors is 0.4-0.5°) which would enable users to receive high data rate. This proposed system overcomes deficiencies of current generation state of the art communication systems by providing much lower level of phase deviation error which would result in much higher modulation schemes and high data rate.

16. 发明申请

US20160315628A1 Frequency Generator with Two Voltage Controlled Oscillators 审中-公开
标题翻译：带两个压控振荡器的频率发生器
公开(公告)号：US20160315628A1
公开(公告)日：2016-10-27
申请号：US15132678
申请日：2016-04-19
申请人： Endress + Hauser GmbH + Co. KG
发明人： Winfried Mayer , Martin Hitzler , Christian Waldschmidt
IPC分类号： H03L7/23 , G01S13/32 , H03L7/099 , H03L7/185 , H03L7/093 , G01F23/284 , H03L7/197
CPC分类号： H03L7/23 , G01F23/284 , G01S7/35 , G01S13/345 , G01S13/88 , H03L7/099 , H03L7/1976 , H03L2207/06
摘要： Described is a frequency generator for producing a frequency ramp. The frequency generator includes a first voltage controlled oscillator, which has a plurality of switchable sub-bands and is designed to produce a first frequency signal, wherein a switching from one sub-band to a neighboring sub-band occurs at predetermined first switching locations, as well as a second voltage controlled oscillator, which has a plurality of switchable sub-bands and is designed to produce a second frequency signal. A switching from one sub-band to a neighboring sub-band occurs at predetermined second switching locations. The sub-bands of the second voltage controlled oscillator are arranged offset in frequency relative to the sub-bands of the first voltage controlled oscillator. The frequency generator is designed to switch either the first frequency signal or the second frequency signal through to the output of the electronic switch element, and to switch the electronic switch element such that during the producing of the frequency ramp alternately either the first frequency signal or the second frequency signal is switched through to the output of the electronic switch element, wherein, in each case, when at one of the voltage controlled oscillators the switching between two neighboring sub-bands is occurring, the frequency signal produced by the respectively other voltage controlled oscillator is switched through to the output of the electronic switch element.
摘要翻译：描述了用于产生频率斜坡的频率发生器。频率发生器包括第一压控振荡器，其具有多个可切换子带，并被设计为产生第一频率信号，其中在预定的第一切换位置发生从一个子带到相邻子带的切换，以及第二压控振荡器，其具有多个可切换子带并被设计为产生第二频率信号。在预定的第二切换位置发生从一个子带到相邻子带的切换。第二压控振荡器的子带被布置为相对于第一压控振荡器的子带的频率偏移。频率发生器被设计成将第一频率信号或第二频率信号切换到电子开关元件的输出，并且切换电子开关元件，使得在频率斜坡的交替产生期间，第一频率信号或第二频率信号被切换到电子开关元件的输出，其中，在每种情况下，当在一个压控振荡器处于两个相邻子带之间的切换时，发生由相应的其它电压产生的频率信号受控振荡器切换到电子开关元件的输出端。

17. 发明申请

US20160285468A1 VOLTAGE CONTROLLED OSCILLATOR RUNAWAY PREVENTION 有权
公开(公告)号：US20160285468A1
公开(公告)日：2016-09-29
申请号：US14733993
申请日：2015-06-09
申请人： International Business Machines Corporation
发明人： David M. Friend , James D. Strom , Alan P. Wagstaff
IPC分类号： H03L7/14
CPC分类号： H03L7/085 , H03B5/06 , H03K23/42 , H03L3/00 , H03L7/07 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H03L7/22 , H03L7/23
摘要： A feedback module for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit can include a first, a second, and a third input to receive a first output signal from a PLL circuit, a reference signal, and a first control signal. The feedback module may also include a feedback circuit to generate a second control signal, the second control signal being coupled to an input of the PLL circuit, wherein the feedback circuit generates the second control signal by comparing a number of cycles of the first output signal to a first threshold, and a number of cycles of the reference signal to a second threshold.

18. 发明授权

US09325927B2 Method of operating a multi-stream reception scheme 有权
标题翻译：操作多流接收方案的方法
公开(公告)号：US09325927B2
公开(公告)日：2016-04-26
申请号：US12865991
申请日：2009-02-03
申请人： Yann Le Guillou
发明人： Yann Le Guillou
IPC分类号： H04B1/06 , H04N5/455 , H03L7/197 , H03L7/23 , H04N21/61 , H04N21/426
CPC分类号： H04N5/455 , H03L7/1976 , H03L7/23 , H04N21/4263 , H04N21/42676 , H04N21/6118
摘要： A method of operating a multi-stream reception scheme, such as DOCSIS (Data Over Cable Service Interface Specifications), comprising at least two receivers (10, 12, 14) having respective voltage controlled oscillators (16), the method including monitoring a change in local oscillator frequency in a selected one of the at least two streams and, if the frequency distance between the local oscillator frequencies is below a value likely to cause pulling or coupling between the voltage controlled oscillators of the at least two receivers, resetting the frequency planning of the selected one of the at least two streams to maximize the frequency distance of the voltage controlled oscillator of the selected stream with the voltage controlled oscillators of the or the other streams.
摘要翻译：一种操作诸如DOCSIS（Data Over Cable Service Interface Specifications）的多流接收方案的方法，包括至少两个具有各自的压控振荡器（16）的接收器（10,12,14），该方法包括监视变化在所述至少两个流中所选择的一个中的本地振荡器频率中，并且如果所述本地振荡器频率之间的频率距离低于可能导致所述至少两个接收机的压控振荡器之间的拉或耦合的值，则重置所述频率规划所述至少两个流中所选择的一个流，以使所选择的流的压控振荡器的频率距离与所述或其它流的压控振荡器最大化。

19. 发明申请

US20160105188A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160105188A1
公开(公告)日：2016-04-14
申请号：US14837731
申请日：2015-08-27
申请人： JONG-PIL CHO , YOUNG-JOO LEE
发明人： JONG-PIL CHO , YOUNG-JOO LEE
IPC分类号： H03L7/087 , H04L7/00 , H04B5/00 , H04L7/033 , H03L7/089 , H03L7/099
CPC分类号： H03L7/087 , H03L7/0805 , H03L7/0814 , H03L7/18 , H03L7/23 , H04B5/0025 , H04B5/0031 , H04B5/0056 , H04L7/0008
摘要： A semiconductor device including a PLL providing candidate clocks of different phases in response to a first clock received from a reader via an antenna, a phase difference detector detecting a phase difference between the first clock and a clock from the candidate clocks, a phase difference controller that selects another clock from the candidate clocks, and a driver that provides transmission data synchronously with the another clock to the reader.
摘要翻译：一种半导体器件，包括响应于从读取器经由天线接收的第一时钟，提供不同相位的候选时钟的PLL;相位差检测器，检测来自候选时钟的第一时钟和时钟之间的相位差;相位差控制器从候选时钟中选择另一个时钟，以及向读取器提供与另一时钟同步的传输数据的驱动器。

20. 发明申请

US20160072440A1 Digital Calibration for Multiphase Oscillators 有权
标题翻译：多相振荡器的数字校准
公开(公告)号：US20160072440A1
公开(公告)日：2016-03-10
申请号：US14858965
申请日：2015-09-18
申请人： Rambus Inc.
发明人： Mohammad Hekmat , Reza Navid
IPC分类号： H03B27/00 , H03L7/099
CPC分类号： H03B27/00 , H03L7/06 , H03L7/099 , H03L7/23
摘要： A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.
摘要翻译：锁相环电路包括具有多个耦合振荡器的多相振荡器。校准模块在校准过程中检测锁相环电路中的不同振荡器的频率特性之间的不匹配。校准模块然后校准各种振荡器以补偿检测到的失配。一旦校准，尽管不同振荡器之间的频率特性不匹配，锁相环电路可以很少或没有性能下降。

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