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11. 发明申请

US20050110671A1 Dummy delay line based DLL and method for clocking in pipeline ADC 有权
标题翻译：基于虚拟延迟线的DLL和管道ADC中的时钟方法
公开(公告)号：US20050110671A1
公开(公告)日：2005-05-26
申请号：US10887969
申请日：2004-07-09
申请人： Chun Lee , Visvesvaraya Pentakota , Vineet Mishra
发明人： Chun Lee , Visvesvaraya Pentakota , Vineet Mishra
IPC分类号： H03L7/081 , H03L7/089 , H03L7/10 , H03M1/06 , H03M1/08 , H03M1/16 , H03M1/44 , H03M1/38 , H03L7/06
CPC分类号： H03L7/0812 , H03L7/0805 , H03L7/0891 , H03L7/10 , H03L2207/14 , H03M1/0678 , H03M1/0818 , H03M1/167 , H03M1/442
摘要： A delay locked loop clock generation circuit (100) includes a delay locked loop circuit (18), a dummy delay line (40), and a watch dog circuit (32). The delay locked loop circuit includes a delay line (20), a phase detector (25), and a charge pump circuit (30) having an input connected to the output (27) of the phase detector and an output (23) producing a delay control signal (Vctrl) coupled to the stages of the delay line of the delay locked loop circuit. The stages of the delay line are precisely matched to those of the dummy delay line (40). Tap points of the dummy delay line are connected to inputs of the watchdog circuit (32), which operates to generate control signals (34A,B) applied to control the phase detector (25 and the charge pump circuit (30). Tap point.signals of the delay line (20) are decoded to produce clock signals (52) for a pipeline ADC (54).
摘要翻译：延迟锁定环形时钟产生电路（100）包括延迟锁定环电路（18），虚拟延迟线（40）和看门狗电路（32）。延迟锁定环电路包括延迟线（20），相位检测器（25）和电荷泵电路（30），其具有连接到相位检测器的输出端（27）的输入端和产生延迟控制信号（Vctr1）耦合到延迟锁定环路延迟线的级。延迟线的级与虚拟延迟线（40）的级精确匹配。虚拟延迟线的抽头点连接到看门狗电路（32）的输入端，其操作以产生用于控制相位检测器（25和电荷泵电路（30））的控制信号（34A，B）。延迟线（20）的信号被解码以产生用于流水线ADC（54）的时钟信号（52）。

12. 发明申请

US20040239389A1 DLL circuit and camcorder using DLL circuit 有权
标题翻译： DLL电路和摄像机使用DLL电路
公开(公告)号：US20040239389A1
公开(公告)日：2004-12-02
申请号：US10847303
申请日：2004-05-18
申请人： CANON KABUSHIKI KAISHA
发明人： Yasushi Matsuno
IPC分类号： H03L007/06
CPC分类号： H03L7/0812 , H03L2207/14 , H04N5/23212 , H04N5/335
摘要： A DLL circuit which can prevent transition to a pseudo lock state is provided. The DLL circuit includes a delay stage 11 to which a reference clock is input and in which variable delay elements D being able to change an amount of delay are connected in a plurality of stages, a phase comparator (PH Comp) 14 which compares the phase of the reference clock to the phase of one delay signal extracted from the delay stage, and a delay control circuit 12 which performs delay control of the delay element in the delay stage on the basis of the comparison result by the phase-comparison means, and DFF 15 which detects a phase relationship of at least two delay signals extracted from the delay stage to discriminate a state which is not a normal lock state and controls the delay control circuit to perform state transition to the normal lock state.
摘要翻译：提供了可以防止转换到伪锁定状态的DLL电路。 DLL电路包括延迟级11，参考时钟被输入到其中，其中可变延迟元件D能够改变延迟量的多个级连接在一起;相位比较器（PH Comp）14，其将相位基准时钟与从延迟级提取的一个延迟信号的相位相对应的延迟控制电路12，以及延迟控制电路12，根据相位比较装置的比较结果对延迟元件进行延迟控制;以及 DFF15，其检测从延迟级提取的至少两个延迟信号的相位关系，以区分不是正常锁定状态的状态，并且控制延迟控制电路以执行到正常锁定状态的状态转换。

13. 发明申请

US20040008088A1 Phase detector for a delay locked loop and delay locked loop with the phase detector 有权
公开(公告)号：US20040008088A1
公开(公告)日：2004-01-15
申请号：US10444545
申请日：2003-05-23
发明人： Nicola Da Dalt
IPC分类号： H03L007/00
CPC分类号： H03L7/0891 , H03L7/0812 , H03L2207/14
摘要： A phase detector for a delay locked loop with a delay unit that delays a periodic clock signal by a settable delay, has a first input for the periodic clock signal, a second input for the delayed clock signal, an UP output and a DOWN output. The phase detector outputs a first pulse signal at the UP output and a second pulse signal at the DOWN output, which signals can respectively assume a first or a second level, for the setting of the delay unit. The first pulse signal changes to the first level in the event of a positive edge of the clock signal and the second pulse signal changes to the first level in the event of a positive edge of the delayed clock signal. In the event that both pulse signals are at the first level, a reset device resets both pulse signals to the second level. The phase detector has a blocking device which taps off at the delay unit a partly delayed clock signal with a delay that is less than the delayed clock signal, and prevents a resetting of the first pulse signal for at least half a period of the clock signal if a positive edge of the partly delayed clock signal occurs while the first pulse signal is at the first level.

14. 发明申请

US20030193374A1 PLL for clock recovery with initialization sequence 有权
标题翻译： PLL用于具有初始化序列的时钟恢复
公开(公告)号：US20030193374A1
公开(公告)日：2003-10-16
申请号：US10412448
申请日：2003-04-11
发明人： James J. McDonald II , Ronald B. Hulfachor , Jim Wunderlich
IPC分类号： H03B005/18
CPC分类号： H03L7/0891 , H03L7/095 , H03L7/0995 , H03L7/10 , H03L2207/14 , H04L7/033 , H04L7/044 , H04L7/10
摘要： A phase locked loop circuit is used to provide timing clocks for data bit recovery from a serial data flow. The system locks to a SYNC signal, preferably a lower frequency fifty percent duty cycle square wave with a period equal to the time of a fully framed serial data word. When a start signal transition is detected the system is prevented from trying to lock onto the data signal edge transitions. But, the system provides a signal suitable for clocking in the individual data bits.
摘要翻译：使用锁相环电路来提供从串行数据流中进行数据位恢复的定时时钟。该系统锁定到SYNC信号，优选地是具有等于完全成帧的串行数据字的时间的周期的低频百分之五十的占空比方波。当检测到启动信号转换时，系统被阻止试图锁定到数据信号边沿转换。但是，该系统提供适合于在各个数据位中计时的信号。

15. 发明申请

US20020180500A1 Clock generation circuit, control method of clock generation circuit, clock reproducing circuit, semiconductor memory device, and dynamic random access memory 有权
公开(公告)号：US20020180500A1
公开(公告)日：2002-12-05
申请号：US10202091
申请日：2002-07-25
发明人： Yuichi Okuda , Hideo Chigasaki , Hiroki Miyashita
IPC分类号： H03L007/06
CPC分类号： G11C7/222 , G11C7/1051 , H03L7/0814 , H03L2207/14
摘要： A DLL circuit or the like is configured so as to be capable of measuring the optimum number of cycles for a delay amount from the input of an external clock to the output of data through the use of a variable delay circuit and performing lock according to the measured number of cycles, whereby a clock generation circuit having a wide lock range can be implemented regardless of the performance of the variable delay circuit and a clock access time.

16. 发明授权

US06377511B1 Semiconductor integrated circuit device 有权
公开(公告)号：US06377511B1
公开(公告)日：2002-04-23
申请号：US09629173
申请日：2000-07-31
申请人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
发明人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
IPC分类号： G11C700
CPC分类号： H03L7/107 , G11C5/025 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/12 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12005 , H03L7/0814 , H03L7/0898 , H03L7/1072 , H03L2207/14
摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

17. 发明申请

US20020017939A1 Clock generation circuit, control method of clock generation circuit, clock reproducing circuit, semiconductor memory device, and dynamic random access memory 有权
公开(公告)号：US20020017939A1
公开(公告)日：2002-02-14
申请号：US09903830
申请日：2001-07-13
发明人： Yuichi Okuda , Hideo Chigasaki , Hiroki Miyashita
IPC分类号： G06F001/04
CPC分类号： G11C7/222 , G11C7/1051 , H03L7/0814 , H03L2207/14
摘要： A DLL circuit or the like is configured so as to be capable of measuring the optimum number of cycles for a delay amount from the input of an external clock to the output of data through the use of a variable delay circuit and performing lock according to the measured number of cycles, whereby a clock generation circuit having a wide lock range can be implemented regardless of the performance of the variable delay circuit and a clock access time.

18. 发明授权

US06326826B1 Wide frequency-range delay-locked loop circuit 有权
标题翻译：宽频率延迟锁定环路
公开(公告)号：US06326826B1
公开(公告)日：2001-12-04
申请号：US09574571
申请日：2000-05-17
申请人： Kyeongho Lee , Deog-Kyoon Jeong
发明人： Kyeongho Lee , Deog-Kyoon Jeong
IPC分类号： H03L700
CPC分类号： H03L7/087 , H03L7/0812 , H03L7/0891 , H03L7/10 , H03L2207/14
摘要： A delay-locked loop (DLL), including frequency detection logic and a phase detector, is described having an operating range as wide as a conventional charge pump phase locked loop. The frequency detector logic counts the number of rising edges of the multi-phase clocks generated from a reference clock during one period of the reference clock. A loop filter is used to adjust the frequency of each multi-phase clock until frequency lock is obtained by comparing the number of rising edges. After frequency lock, phase detection logic is used to finely tune out the remaining phase error.
摘要翻译：描述了包括频率检测逻辑和相位检测器的延迟锁定环（DLL），其具有与常规电荷泵锁相环一样宽的操作范围。频率检测器逻辑计算在参考时钟的一个周期期间从参考时钟产生的多相时钟的上升沿的数量。环路滤波器用于调整每个多相时钟的频率，直到通过比较上升沿的数量获得频率锁定为止。在频率锁定之后，相位检测逻辑用于微调剩余的相位误差。

19. 发明授权

US06304116B1 Delay locked looped circuits and methods of operation thereof 有权
标题翻译：延迟锁定环路电路及其操作方法
公开(公告)号：US06304116B1
公开(公告)日：2001-10-16
申请号：US09484902
申请日：2000-01-18
申请人： Hong-il Yoon , Chang-sik Yoo
发明人： Hong-il Yoon , Chang-sik Yoo
IPC分类号： H03L706
CPC分类号： H03L7/0812 , H03L7/0891 , H03L2207/14
摘要： The present invention provides delay locked loop circuits, phase detectors and methods for producing a delayed signal from a periodic input signal. An intermediate delay signal as well as an input signal and a delayed output signal are provided to a delay control circuit that controls the delay of a delay circuit based on a comparison of the input signal and output signal following a transition of the intermediate signal. The apparatus and methods of the present invention may thereby be able to distinguish between a case in which tTOTAL=T and tTOTAL=2T to reduce the potential for locking in a false state.
摘要翻译：本发明提供延迟锁定环路电路，相位检测器和用于从周期性输入信号产生延迟信号的方法。中间延迟信号以及输入信号和延迟输出信号被提供给延迟控制电路，该延迟控制电路基于中间信号转换之后的输入信号和输出信号的比较来控制延迟电路的延迟。因此，本发明的装置和方法能够区分tTOTAL = T和tTOTAL = 2T的情况，以减少在假状态下锁定的可能性。

20. 发明授权

US06249165B1 Interlaced delay-locked loops for controlling memory-circuit timing 失效
标题翻译：用于控制存储器电路时序的隔行延迟锁定环路
公开(公告)号：US06249165B1
公开(公告)日：2001-06-19
申请号：US09259625
申请日：1999-02-26
申请人： Ronnie M. Harrison
发明人： Ronnie M. Harrison
IPC分类号： H03H1126
CPC分类号： H03L7/0805 , H03K5/133 , H03K5/135 , H03K5/26 , H03L7/07 , H03L7/0812 , H03L7/0896 , H03L7/10 , H03L2207/14
摘要： In digital circuits, such as memory circuits, it is sometimes necessary to delay one signal a precise amount of time relative a reference signal. One way to do this is to feed the reference signal to a delay-locked loop which generates a set of signals, each delayed a different amount relative the reference signal. However, as circuits get faster and faster, conventional delay-locked loops require the addition of extra interpolation circuitry to generate smaller delays, and thus consume considerable power and circuit space. Accordingly, the inventor devised a circuit which interlaces and synchronizes two delay-locked loops, each including a number of controllable delay elements linked in a chain. In one embodiment, the first loop produces a sequence of clock signals delayed an even number of delay periods relative a reference clock signal, and the second loop produces a sequence of clock signals delayed an odd number of delay periods relative the reference clock signal. In addition, the first and second loops are synchronized.
摘要翻译：在诸如存储器电路的数字电路中，有时需要相对于参考信号延迟一个信号精确的时间量。一种这样做的方法是将参考信号馈送到延迟锁定环路，该环路产生一组信号，每个信号相对于参考信号延迟不同的量。然而，随着电路越来越快，传统的延迟锁定环路需要额外的内插电路来产生更小的延迟，从而消耗相当大的功率和电路空间。因此，发明人设计了一种电路，其将两个延迟锁定环交错并同步，每个延迟锁定环包括链接在一起的多个可控延迟元件。在一个实施例中，第一循环产生相对于参考时钟信号延迟偶数个延迟周期的时钟信号序列，并且第二循环产生相对于参考时钟信号延迟奇数个延迟周期的时钟信号序列。此外，第一和第二循环是同步的。

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