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11. 发明申请

US20170084752A1 SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF 审中-公开
公开(公告)号：US20170084752A1
公开(公告)日：2017-03-23
申请号：US15342380
申请日：2016-11-03
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Georgios Vellianitis
IPC分类号： H01L29/786 , H01L29/66 , H01L21/8238 , H01L29/423 , H01L27/092
CPC分类号： H01L29/78618 , H01L21/823487 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823885 , H01L27/092 , H01L29/41741 , H01L29/42392 , H01L29/66356 , H01L29/66666 , H01L29/7391 , H01L29/7788 , H01L29/78642 , H01L29/78696
摘要： A semiconductor arrangement and methods of formation are provided. A semiconductor arrangement includes a semiconductor column on a buffer layer over a substrate. The buffer layer comprises a conductive material. Both a first end of the semiconductor column and a bottom contact are connected to a buffer layer such that the first end of the semiconductor column and the bottom contact are connected to one another through the buffer layer, which reduces a contact resistance between the semiconductor column and the bottom contact. A second end of the semiconductor column is connected to a top contact. In some embodiments, the first end of the semiconductor column corresponds to a source or drain of a transistor and the second end corresponds to the drain or source of the transistor.

12. 发明申请

US20160380091A1 NITRIDE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：氮化物半导体器件
公开(公告)号：US20160380091A1
公开(公告)日：2016-12-29
申请号：US15149528
申请日：2016-05-09
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA
发明人： Takashi OKAWA
IPC分类号： H01L29/778 , H01L29/45 , H01L29/47
CPC分类号： H01L29/452 , H01L29/0646 , H01L29/1066 , H01L29/2003 , H01L29/42316 , H01L29/475 , H01L29/7786 , H01L29/7788
摘要： A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer located on the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; a p-type semiconductor layer located on the second nitride semiconductor layer; and a gate electrode located on the p-type semiconductor layer. A first interface and a second interface are located in parallel between the gate electrode and the p-type semiconductor layer. The first interface has a first barrier with respect to holes moving in a direction from the p-type semiconductor layer to the gate electrode. The second interface has a second barrier with respect to the holes moving in a direction from the p-type semiconductor layer to the gate electrode. The second barrier is higher than the first barrier.
摘要翻译：氮化物半导体器件包括：第一氮化物半导体层; 位于所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层的带隙大的带隙的第二氮化物半导体层; 位于所述第二氮化物半导体层上的p型半导体层; 以及位于p型半导体层上的栅电极。第一接口和第二接口位于栅电极和p型半导体层之间并联。第一界面相对于从p型半导体层向栅电极的方向移动的孔具有第一屏障。第二界面相对于在从p型半导体层到栅电极的方向上移动的孔具有第二阻挡层。第二个障碍高于第一个障碍。

13. 发明申请

US20160365439A1 Vertical Semiconductor Device Structure and Method of Forming 审中-公开
标题翻译：立式半导体器件结构及其成型方法
公开(公告)号：US20160365439A1
公开(公告)日：2016-12-15
申请号：US14739450
申请日：2015-06-15
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yi-Hsiung Lin , Yi-Hsun Chiu
IPC分类号： H01L29/78 , H01L29/417 , H01L29/423 , H01L29/66
CPC分类号： H01L29/42392 , H01L29/1083 , H01L29/456 , H01L29/66666 , H01L29/775 , H01L29/7788 , H01L29/7827 , H01L29/78642
摘要： Vertical gate all-around (VGAA) structures are described. In an embodiment, a structure including a first doped region in a substrate, a first vertical channel extending from the first doped region, a first metal-semiconductor compound region in a top surface of the first doped region, the first metal-semiconductor compound region extending along at least two sides of the first vertical channel, and a first gate electrode around the first vertical channel.
摘要翻译：描述了垂直门全能（VGAA）结构。在一个实施例中，包括衬底中的第一掺杂区域，从第一掺杂区域延伸的第一垂直沟道，第一掺杂区域的顶表面中的第一金属 - 半导体化合物区域，第一金属 - 半导体化合物区域沿着第一垂直通道的至少两侧延伸，以及围绕第一垂直通道的第一栅电极。

14. 发明申请

US20160260723A1 Integrated Circuitry Components, Switches, and Memory Cells 有权
标题翻译：集成电路组件，开关和存储单元
公开(公告)号：US20160260723A1
公开(公告)日：2016-09-08
申请号：US15155289
申请日：2016-05-16
申请人： Micron Technology, Inc.
发明人： Gurtej S. Sandhu
IPC分类号： H01L27/115 , H01L29/16
CPC分类号： H01L27/1159 , B82Y10/00 , G11C11/221 , H01L27/11521 , H01L29/1606 , H01L29/513 , H01L29/516 , H01L29/7788 , H01L29/78391
摘要： A switch includes a graphene structure extending longitudinally between a pair of electrodes and being conductively connected to both electrodes of said pair. First and second electrically conductive structures are laterally outward of the graphene structure and on opposing sides of the graphene structure from one another. Ferroelectric material is laterally between the graphene structure and at least one of the first and second electrically conductive structures. The first and second electrically conductive structures are configured to provide the switch into “on” and “off” states by application of an electric field across the graphene structure and the ferroelectric material. Other embodiments are disclosed, including components of integrated circuitry which may not be switches.
摘要翻译：开关包括在一对电极之间纵向延伸并且导电地连接到所述对的两个电极的石墨烯结构。第一和第二导电结构在石墨烯结构的横向外侧和石墨烯结构的相对侧彼此之间。铁电材料横向在石墨烯结构和第一和第二导电结构中的至少一个之间。第一和第二导电结构被配置为通过在整个石墨烯结构和铁电材料上施加电场来将开关提供到“导通”和“关闭”状态。公开了其他实施例，包括可以不是开关的集成电路的部件。

15. 发明申请

US20160197174A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160197174A1
公开(公告)日：2016-07-07
申请号：US14911680
申请日：2014-09-08
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA
发明人： Masakazu KANECHIKA , Makoto KUWAHARA , Hiroyuki UEDA , Hidemoto TOMITA
IPC分类号： H01L29/778 , H01L21/02 , H01L29/66 , H01L29/06 , H01L29/20 , H01L29/205
CPC分类号： H01L29/7783 , H01L21/0242 , H01L21/02458 , H01L21/02502 , H01L21/0254 , H01L21/02579 , H01L29/0646 , H01L29/0684 , H01L29/1066 , H01L29/2003 , H01L29/205 , H01L29/34 , H01L29/66462 , H01L29/7786 , H01L29/7788
摘要： A semiconductor device includes a first compound semiconductor layer, a second compound semiconductor layer having a larger band gap than that of the first compound semiconductor layer, p-type third compound semiconductor layer disposed above a portion of the second compound semiconductor layer, a p-type fourth compound semiconductor layer disposed above the third compound semiconductor layer and having a higher resistance than that of the third compound semiconductor layer, and a gate electrode disposed above the fourth compound semiconductor layer.
摘要翻译：半导体器件包括第一化合物半导体层，具有比第一化合物半导体层的带隙大的带隙的第二化合物半导体层，配置在第二化合物半导体层的一部分上方的p型第三化合物半导体层，所述第四化合物半导体层配置在所述第三化合物半导体层的上方，具有比所述第三化合物半导体层高的电阻，以及设置在所述第四化合物半导体层的上方的栅电极。

16. 发明授权

US09362389B2 Polarization induced doped transistor 有权
标题翻译：极化感应掺杂晶体管
公开(公告)号：US09362389B2
公开(公告)日：2016-06-07
申请号：US14470569
申请日：2014-08-27
申请人： University of Notre Dame du Lac
发明人： Huili (Grace) Xing , Debdeep Jena , Kazuki Nomoto , Bo Song , Mingda Zhu , Zongyang Hu
IPC分类号： H01L29/778 , H01L29/20 , H01L29/201 , H01L29/205 , H01L29/06 , H01L29/10 , H01L29/808
CPC分类号： H01L29/7787 , H01L21/26546 , H01L21/3245 , H01L21/7813 , H01L29/0619 , H01L29/0843 , H01L29/1095 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/41758 , H01L29/517 , H01L29/7786 , H01L29/7788 , H01L29/8083
摘要： A nitride-based field effect transistor (FET) comprises a compositionally graded and polarization induced doped p-layer underlying at least one gate contact and a compositionally graded and doped n-channel underlying a source contact. The n-channel is converted from the p-layer to the n-channel by ion implantation, a buffer underlies the doped p-layer and the n-channel, and a drain underlies the buffer.
摘要翻译：基于氮化物的场效应晶体管（FET）包括在源极触点下面的至少一个栅极接触和成分渐变和掺杂的n沟道的组成梯度和极化诱导掺杂p层。通过离子注入将n沟道从p层转换成n沟道，缓冲器位于掺杂p层和n沟道的下面，漏极位于缓冲器的下面。

17. 发明申请

US20160118487A1 Transistors, Semiconductor Devices, and Methods of Manufacture Thereof 审中-公开
标题翻译：晶体管，半导体器件及其制造方法
公开(公告)号：US20160118487A1
公开(公告)日：2016-04-28
申请号：US14977112
申请日：2015-12-21
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Gerben Doornbos , Richard Kenneth Oxland
IPC分类号： H01L29/778 , H01L29/205
CPC分类号： H01L29/7786 , H01L21/182 , H01L29/205 , H01L29/66545 , H01L29/7788 , H01L29/78681
摘要： Transistors, semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a transistor over a workpiece. The transistor includes a sacrificial gate material comprising a group III-V material. The method includes combining a metal (Me) with the group III-V material of the sacrificial gate material to form a gate of the transistor comprising a Me-III-V compound material.
摘要翻译：公开了晶体管，半导体器件及其制造方法。在一个实施例中，制造半导体器件的方法包括在工件上形成晶体管。晶体管包括包含III-V族材料的牺牲栅极材料。该方法包括将金属（Me）与牺牲栅极材料的III-V族材料组合以形成包含Me-III-V复合材料的晶体管的栅极。

18. 发明申请

US20160118377A1 METHOD OF FORMING A HIGH ELECTRON MOBILITY SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR 有权
标题翻译：形成高电子移动半导体器件及其结构的方法
公开(公告)号：US20160118377A1
公开(公告)日：2016-04-28
申请号：US14989370
申请日：2016-01-06
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Peter Moens , Jaume Roig Guitart
IPC分类号： H01L27/06 , H01L29/205 , H01L23/31 , H01L29/423 , H01L29/78 , H01L23/495 , H01L29/20 , H01L29/778
CPC分类号： H01L27/0617 , H01L21/8252 , H01L23/3107 , H01L23/49503 , H01L23/49562 , H01L23/49575 , H01L27/0605 , H01L29/1087 , H01L29/2003 , H01L29/205 , H01L29/407 , H01L29/4175 , H01L29/41766 , H01L29/41775 , H01L29/4236 , H01L29/66431 , H01L29/66462 , H01L29/7786 , H01L29/7787 , H01L29/7788 , H01L29/7827 , H01L29/872 , H01L2224/0603 , H01L2224/48247 , H01L2924/12032 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： In one embodiment, a method of forming a semiconductor device can comprise; forming a HEM device on a semiconductor substrate. The semiconductor substrate provides a current carrying electrode for the semiconductor device and one or more internal conductor structures provide a vertical current path between the semiconductor substrate and regions of the HEM device.
摘要翻译：在一个实施例中，形成半导体器件的方法可以包括：在半导体衬底上形成HEM器件。半导体衬底提供用于半导体器件的载流电极，并且一个或多个内部导体结构在半导体衬底和HEM器件的区域之间提供垂直电流路径。

19. 发明授权

US09318572B2 Ambipolar synaptic devices 有权
公开(公告)号：US09318572B2
公开(公告)日：2016-04-19
申请号：US14846750
申请日：2015-09-05
申请人： International Business Machines Corporation
发明人： Ali Afzali-Ardakani , Tze-Chiang Chen , Kailash Gopalakrishnan , Bahman Hekmatshoartabari
IPC分类号： H01L21/20 , H01L29/66 , H01L29/06 , H01L29/10 , H01L29/12 , H01L21/8238
CPC分类号： H01L51/0566 , G06N3/063 , G06N3/0635 , G11C11/54 , H01L21/28273 , H01L21/8238 , H01L29/0649 , H01L29/0665 , H01L29/0673 , H01L29/0843 , H01L29/0847 , H01L29/1029 , H01L29/1054 , H01L29/122 , H01L29/125 , H01L29/127 , H01L29/165 , H01L29/267 , H01L29/42324 , H01L29/432 , H01L29/51 , H01L29/66431 , H01L29/66462 , H01L29/66477 , H01L29/7783 , H01L29/7786 , H01L29/7788 , H01L29/7881 , H01L51/0055 , H01L51/0541 , H01L51/0545 , H01L51/0562 , H01L2251/301
摘要： Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.

20. 发明申请

US20150364599A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150364599A1
公开(公告)日：2015-12-17
申请号：US14644080
申请日：2015-03-10
申请人： Kabushiki Kaisha Toshiba
发明人： Tetsuya Ohno
IPC分类号： H01L29/78 , H01L29/20 , H01L29/66
CPC分类号： H01L29/7827 , H01L29/0646 , H01L29/0657 , H01L29/1066 , H01L29/2003 , H01L29/41741 , H01L29/42316 , H01L29/66446 , H01L29/66462 , H01L29/7788
摘要： In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type or an intrinsic type, and a second semiconductor layer of a second conductivity type provided on the first semiconductor layer. The device further includes a third semiconductor layer of the first conductivity type or an intrinsic type provided on the second semiconductor layer. The device further includes a control electrode and a first electrode provided on a side portion of the first, second or third semiconductor layer through at least one insulating layer, and a second electrode provided on the third semiconductor layer.
摘要翻译：在一个实施例中，半导体器件包括第一导电类型或固有类型的第一半导体层，以及设置在第一半导体层上的第二导电类型的第二半导体层。该器件还包括第一导电类型的第三半导体层或设置在第二半导体层上的固有类型。该装置还包括控制电极和通过至少一个绝缘层设置在第一，第二或第三半导体层的侧部上的第一电极和设置在第三半导体层上的第二电极。

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