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11. 发明授权

US09513333B2 Test interface board and test system including the same 有权
标题翻译：测试接口板和测试系统包括相同
公开(公告)号：US09513333B2
公开(公告)日：2016-12-06
申请号：US14458241
申请日：2014-08-12
申请人： Samsung Electronics Co., Ltd.
发明人： Ki-Jae Song , Jong-woon Yoo
IPC分类号： G01R31/00 , G01R31/30 , G01R31/28 , G11C29/56 , G11C5/14
CPC分类号： G01R31/3004 , G01R31/2839 , G01R31/2889 , G11C5/147 , G11C29/56 , G11C2029/5602
摘要： A test interface board includes a substrate including a power plane electrically connected to at least one power terminal of a semiconductor device under test, and a ground plane electrically connected to at least one ground terminal of the semiconductor device under test, and a voltage regulator arranged on the substrate and configured to supply, via the power plane and the ground plane, to the semiconductor device under test, a driving voltage.
摘要翻译：测试接口板包括：基板，包括电连接到被测半导体器件的至少一个电源端子的电源平面;以及电连接到被测半导体器件的至少一个接地端子的接地平面;以及电压调节器，在基板上并经配置以经由电源平面和接地平面向被测半导体器件提供驱动电压。

12. 发明申请

US20160284426A1 ARBITRATION FOR MEMORY DIAGNOSTICS 审中-公开
标题翻译：用于记忆诊断的仲裁
公开(公告)号：US20160284426A1
公开(公告)日：2016-09-29
申请号：US14669056
申请日：2015-03-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Aravindan J. BUSI , Kevin W. GORMAN , Deepak I. HANAGANDI , Kiran K. NARAYAN , Michael R. OUELLETTE
IPC分类号： G11C29/44 , G11C29/38
CPC分类号： G11C29/56008 , G01R31/3187 , G11C29/12 , G11C29/44 , G11C29/4401 , G11C2029/0401 , G11C2029/2602 , G11C2029/5602 , G11C2029/5606
摘要： A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.
摘要翻译：提供了用于存储器诊断的串行仲裁及其方法。该方法包括并行地在多个存储器上运行内置自检（BIST）。该方法还包括：在检测到多个存储器的故障存储器时，触发仲裁逻辑将故障存储器的数据移位到芯片焊盘。

13. 发明授权

US09349488B2 Semiconductor memory apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US09349488B2
公开(公告)日：2016-05-24
申请号：US14495988
申请日：2014-09-25
申请人： SK hynix Inc.
发明人： Chang Hyun Lee , Young Jun Ku
IPC分类号： G11C29/56 , G11C29/02 , G11C29/50 , G11C29/12
CPC分类号： G11C29/12015 , G11C29/023 , G11C29/08 , G11C29/12 , G11C29/26 , G11C29/50012 , G11C29/56 , G11C2029/2602 , G11C2029/5602
摘要： A semiconductor memory apparatus includes a plurality of data storage regions; a first internal circuit configured to input a plurality of control signals to the plurality of data storage regions; and a second internal circuit configured to control input timing of a test control signal, and input the test control signal to the plurality of data storage regions according to the controlled input timing in response to a test mode signal.
摘要翻译：半导体存储装置包括多个数据存储区域; 第一内部电路，被配置为将多个控制信号输入到所述多个数据存储区域; 以及第二内部电路，被配置为控制测试控制信号的输入定时，并且响应于测试模式信号，根据受控的输入定时将测试控制信号输入到多个数据存储区域。

14. 发明申请

US20160086678A1 MEMORY TESTING SYSTEM 有权
标题翻译：内存测试系统
公开(公告)号：US20160086678A1
公开(公告)日：2016-03-24
申请号：US14495506
申请日：2014-09-24
申请人： Apple Inc.
发明人： Dragos F. Botea , Bibo Li , Vijay M. Bettada
IPC分类号： G11C29/12
CPC分类号： G11C29/12 , G11C7/00 , G11C7/10 , G11C8/00 , G11C29/021 , G11C29/08 , G11C29/14 , G11C2029/5602
摘要： Techniques are disclosed relating to memory testing. In one embodiment, an integrated circuit is disclosed that includes a memory and an interface circuit. The interface circuit is configured to receive one or more testing signals from a built in self-test (BIST) unit. The interface circuit is further configured to receive, independently from the one or more testing signals, one or more configuration signals from automated test equipment (ATE). The interface circuit is further configured to issue one or more instruction signals to the memory based on the one or more testing signals and based on the one or more configuration signals. In some embodiments, the interface circuit is configured to enable the BIST unit to detect errors in functions the BIST unit is not designed to test.
摘要翻译：公开了与记忆测试相关的技术。在一个实施例中，公开了一种集成电路，其包括存储器和接口电路。接口电路被配置为从内置的自检（BIST）单元接收一个或多个测试信号。接口电路还被配置为独立于一个或多个测试信号接收来自自动测试设备（ATE）的一个或多个配置信号。接口电路还被配置为基于一个或多个测试信号并且基于一个或多个配置信号向存储器发出一个或多个指令信号。在一些实施例中，接口电路被配置为使得BIST单元能够检测BIST单元不被设计用于测试的功能中的错误。

15. 发明授权

US09281080B2 Staged buffer caching in a system for testing a device under test 有权
标题翻译：用于测试被测设备的系统中的分段缓冲区缓存
公开(公告)号：US09281080B2
公开(公告)日：2016-03-08
申请号：US14205086
申请日：2014-03-11
申请人： Advantest Corporation
发明人： Michael Jones , Edmundo Delapuente , Alan S. Krech, Jr.
IPC分类号： G01R31/28 , G11C29/10 , G11C29/56 , G01R31/3183
CPC分类号： G11C29/10 , G01R31/318307 , G01R31/318342 , G11C29/56 , G11C29/56004 , G11C2029/5602
摘要： A system for testing a device under test (DUT) includes a test controller unit that includes a first memory operable to store a data pattern; a bridge circuit that includes a second memory that is smaller than the first memory, and a functional unit that includes a third memory that is smaller than the second memory. Portions of the data pattern are selectively transferred from the first memory to the second memory during and for DUT testing operations. The functional circuit interfaces with the DUT for testing. Portions of the data pattern are selectively transferred from the second memory to the third memory for application to the DUT.
摘要翻译：一种用于测试被测设备（DUT）的系统，包括测试控制器单元，其包括可操作以存储数据模式的第一存储器; 包括比第一存储器小的第二存储器的桥接电路，以及包括小于第二存储器的第三存储器的功能单元。在DUT测试操作期间和数据模式的部分被选择性地从第一存储器传送到第二存储器。功能电路与DUT进行接口测试。将数据模式的一部分从第二存储器选择性地传送到第三存储器以供应用于DUT。

16. 发明申请

US20150332787A1 SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器
公开(公告)号：US20150332787A1
公开(公告)日：2015-11-19
申请号：US14495988
申请日：2014-09-25
申请人： SK hynix Inc.
发明人： Chang Hyun LEE , Young Jun KU
IPC分类号： G11C29/12
CPC分类号： G11C29/12015 , G11C29/023 , G11C29/08 , G11C29/12 , G11C29/26 , G11C29/50012 , G11C29/56 , G11C2029/2602 , G11C2029/5602
摘要： A semiconductor memory apparatus includes a plurality of data storage regions; a first internal circuit configured to input a plurality of control signals to the plurality of data storage regions; and a second internal circuit configured to control input timing of a test control signal, and input the test control signal to the plurality of data storage regions according to the controlled input timing in response to a test mode signal.
摘要翻译：半导体存储装置包括多个数据存储区域; 第一内部电路，被配置为将多个控制信号输入到所述多个数据存储区域; 以及第二内部电路，被配置为控制测试控制信号的输入定时，并且响应于测试模式信号，根据受控的输入定时将测试控制信号输入到多个数据存储区域。

17. 发明授权

US09173293B2 Memory module and video camera 有权
标题翻译：内存模块和摄像机
公开(公告)号：US09173293B2
公开(公告)日：2015-10-27
申请号：US13406892
申请日：2012-02-28
申请人： Yasuyuki Nagahara , Isao Ozawa
发明人： Yasuyuki Nagahara , Isao Ozawa
IPC分类号： G06F12/00 , H05K1/18 , G06F17/50 , G06F12/02 , G11C29/48 , G11C5/04 , G11C16/00 , G11C29/56 , H05K1/02
CPC分类号： G11C5/025 , G06F12/0246 , G06F17/5045 , G06F17/5068 , G06F17/5072 , G06F17/5077 , G06F17/5081 , G11C5/04 , G11C16/00 , G11C29/48 , G11C2029/5602 , H05K1/0268 , H05K1/181 , H05K2201/10159 , H05K2201/10189 , H05K2201/10545 , H05K2203/162 , Y02P70/611
摘要： According to the embodiments, there are provided semiconductor memories that are mounted individually on two sides of a mounting board; a controller that is mounted either on an obverse side or a reverse side of the mounting board, and performs read and write control of the semiconductor memories; and a connector that is deviated in a lateral direction from the controller so as not to overlap the controller, is mounted either on the obverse side or the reverse side of the mounting board, and transfers a signal exchanged between the controller and outside.
摘要翻译：根据实施例，提供了分别安装在安装板的两侧上的半导体存储器; 控制器，其安装在安装板的正面或反面上，并且执行对半导体存储器的读取和写入控制; 并且在控制器的横向上偏离控制器而不与控制器重叠的连接器安装在安装板的正面或反面上，并且传送在控制器和外部之间交换的信号。

18. 发明申请

US20150257255A1 CIRCUIT BOARD HAVING BYPASS PAD 审中-公开
公开(公告)号：US20150257255A1
公开(公告)日：2015-09-10
申请号：US14719321
申请日：2015-05-22
申请人： Samsung Electronics Co., Ltd.
发明人： Sang-Guk Han , Seok-Joon Moon , Beom-jun Jin
IPC分类号： H05K1/02 , G11C29/04 , G11C5/02 , G11C5/06 , H05K1/11 , H05K1/18
CPC分类号： H01L25/0657 , G01R31/2808 , G01R31/2818 , G11C5/02 , G11C5/025 , G11C5/06 , G11C29/04 , G11C29/12 , G11C29/56 , G11C29/56016 , G11C2029/5602 , H01L22/30 , H01L22/32 , H01L23/49811 , H01L23/49838 , H01L23/538 , H01L24/09 , H01L24/48 , H01L24/49 , H01L24/80 , H01L25/0652 , H01L25/0655 , H01L25/18 , H01L2224/05554 , H01L2224/0603 , H01L2224/0912 , H01L2224/48145 , H01L2224/48227 , H01L2224/4912 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/06568 , H01L2225/06596 , H01L2924/00014 , H01L2924/01068 , H01L2924/181 , H05K1/0268 , H05K1/111 , H05K1/117 , H05K1/181 , H05K3/002 , H05K3/245 , H05K3/28 , H05K3/288 , H05K3/323 , H05K2201/0187 , H05K2201/035 , H05K2201/09036 , H05K2201/09472 , H05K2201/099 , H05K2201/10159 , H05K2203/162 , Y10T29/49117 , Y10T29/49155 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.

19. 发明申请

US20150243371A1 CIRCUIT BOARD HAVING BYPASS PAD 审中-公开
公开(公告)号：US20150243371A1
公开(公告)日：2015-08-27
申请号：US14705971
申请日：2015-05-07
申请人： Samsung Electronics Co., Ltd.
发明人： Sang-Guk Han , Seok-Joon Moon , Beom-jun Jin
IPC分类号： G11C29/12 , G01R31/28 , H01L25/065 , H01L23/498 , G11C5/02 , H01L25/18
CPC分类号： H01L25/0657 , G01R31/2808 , G01R31/2818 , G11C5/02 , G11C5/025 , G11C5/06 , G11C29/04 , G11C29/12 , G11C29/56 , G11C29/56016 , G11C2029/5602 , H01L22/30 , H01L22/32 , H01L23/49811 , H01L23/49838 , H01L23/538 , H01L24/09 , H01L24/48 , H01L24/49 , H01L24/80 , H01L25/0652 , H01L25/0655 , H01L25/18 , H01L2224/05554 , H01L2224/0603 , H01L2224/0912 , H01L2224/48145 , H01L2224/48227 , H01L2224/4912 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/06568 , H01L2225/06596 , H01L2924/00014 , H01L2924/01068 , H01L2924/181 , H05K1/0268 , H05K1/111 , H05K1/117 , H05K1/181 , H05K3/002 , H05K3/245 , H05K3/28 , H05K3/288 , H05K3/323 , H05K2201/0187 , H05K2201/035 , H05K2201/09036 , H05K2201/09472 , H05K2201/099 , H05K2201/10159 , H05K2203/162 , Y10T29/49117 , Y10T29/49155 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.

20. 发明授权

US09026854B2 Method of testing universal flash storage (UFS) interface and memory device implementing method of testing UFS interface 有权
标题翻译：通用闪存存储（UFS）接口和内存设备实现UFS接口测试方法的测试方法
公开(公告)号：US09026854B2
公开(公告)日：2015-05-05
申请号：US13647415
申请日：2012-10-09
申请人： Samsung Electronics Co., Ltd.
发明人： Ha-Neul Jeong , Woo-Seong Cheong
IPC分类号： G06F11/00 , G11C29/02 , G06F11/22 , G11C29/56
CPC分类号： G11C29/022 , G06F11/221 , G11C2029/5602
摘要： A method is provided for performing a self-test on a memory device in a test mode, where the memory device includes a universal flash storage (UFS) link layer and a UFS physical layer having a transmitting unit and a receiving unit. The method includes generating a first signal; sending the first signal from a test unit through the UFS link layer to the transmitting unit in the UFS physical layer to be transmitted to the receiving unit; receiving a second signal at the test unit from the receiving unit in the UFS physical layer through the UFS link layer, the second signal being the first signal received by the receiving unit; and testing an operation performed by at least one of the UFS physical layer and the UFS link layer based on the first signal and the second signal.
摘要翻译：提供了一种用于在测试模式下对存储器件执行自检的方法，其中存储器件包括通用闪存存储（UFS）链路层和具有发送单元和接收单元的UFS物理层。该方法包括产生第一信号; 将来自测试单元的第一信号通过UFS链路层发送到UFS物理层中的发送单元以发送到接收单元; 通过UFS链路层从UFS物理层的接收单元在测试单元处接收第二信号，第二信号是由接收单元接收的第一信号; 以及基于所述第一信号和所述第二信号来测试由所述UFS物理层和所述UFS链路层中的至少一个执行的操作。

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