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11. 发明授权

US3372269A Multiplier for simultaneously generating partial products of various bits of the multiplier 失效
标题翻译：用于同时生成乘法器各个位的部分乘积的乘数
公开(公告)号：US3372269A
公开(公告)日：1968-03-05
申请号：US51101365
申请日：1965-10-22
申请人： IBM
发明人： MACSORLEY OLIN L , BIELAWA FRANK R
IPC分类号： G06F7/52
CPC分类号： G06F7/5336

12. 发明授权

US09703531B2 Multiplication of first and second operands using redundant representation 有权
公开(公告)号：US09703531B2
公开(公告)日：2017-07-11
申请号：US14939469
申请日：2015-11-12
申请人： ARM LIMITED
发明人： David Raymond Lutz , Neil Burgess , Christopher Neal Hinds
IPC分类号： G06F7/533 , G06F7/544
CPC分类号： G06F7/5443 , G06F7/50 , G06F7/5324 , G06F7/5336
摘要： A method is provided for multiplying a first operand comprising at least two X-bit portions and a second operand comprising at least one Y-bit portion. At least two partial products are generated, each partial product comprising a product of a selected X-bit portion of the first operand and a selected Y-bit portion of the second operand. Each partial product is converted to a redundant representation in dependence on significance indicating information indicative of a significance of the partial product. In the redundant representation, the partial product is represented using a number of N-bit portions, and in a group of at least two adjacent N-bit portions, a number of overlap bits of a lower N-bit portion of the group have a same significance as some least significant bits of at least one upper N-bit portion of the group. The partial products are added while represented in the redundant representation.

13. 发明申请

US20150193203A1 EFFICIENCY IN A FUSED FLOATING-POINT MULTIPLY-ADD UNIT 审中-公开
标题翻译：熔融浮点添加单元的效率
公开(公告)号：US20150193203A1
公开(公告)日：2015-07-09
申请号：US14149647
申请日：2014-01-07
申请人： NVIDIA CORPORATION
发明人： Srinivasan (Vasu) IYER , David Conrad TANNENBAUM , Stuart F. OBERMAN
IPC分类号： G06F7/544 , G06F7/50
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/5336
摘要： A four cycle fused floating point multiply-add unit includes a radix 8 Booth encoder multiplier that is partitioned over two stages with the compression element allocated to the second stage. The unit further includes an improved shifter design. Processing logic analyzes the input operands, detects values of zero and one, and inhibits portions of the processing logic accordingly. When one of the multiplicand inputs has a value of zero or one, the required multiplication becomes trivial, and the unit inhibits the associated coding logic and data transfer to reduce power consumption. The unit then performs an add-only operation. When the addend input has a value of zero, the addition becomes trivial, and the unit inhibits the improved shifter and data transfer to further reduce power consumption. The unit then performs a multiply-only operation.
摘要翻译：四循环融合浮点乘法单元包括一个基数8布斯编码器乘法器，其在压缩元件分配给第二阶段的两个阶段上被划分。该单元还包括改进的换档器设计。处理逻辑分析输入操作数，检测零和一的值，并相应地禁止处理逻辑的部分。当其中一个被乘数输入值为零或1时，所需的乘法变得微不足道，并且该单元禁止相关编码逻辑和数据传输以降低功耗。该单元然后执行加法运算。当加数输入的值为零时，加法变得微不足道，该单元禁止改进的移位器和数据传输，以进一步降低功耗。该单元然后执行多次操作。

14. 发明授权

US08892621B2 Implementation of negation in a multiplication operation without post-incrementation 有权
标题翻译：在没有后递增的情况下执行乘法运算中的否定
公开(公告)号：US08892621B2
公开(公告)日：2014-11-18
申请号：US13330436
申请日：2011-12-19
申请人： Leonid Dubrovin , Alexander Rabinovitch
发明人： Leonid Dubrovin , Alexander Rabinovitch
IPC分类号： G06F7/533
CPC分类号： G06F7/5336
摘要： A multiplier circuit for generating a product of at least first and second multiplicands includes encoding circuitry comprising a plurality of encoders. Each of the encoders is operative to receive at least a subset of bits of the first multiplicand and to generate a partial product corresponding to the subset of bits of the first multiplicand. The encoding circuitry is further operative to incorporate a negation of the product as a function of at least a first control signal supplied to the multiplier circuit. The multiplier circuit further includes summation circuitry coupled with the encoding circuitry. The summation circuitry is operative to sum each of the partial products generated by the encoding circuitry to thereby generate the product without performing post-incrementation.
摘要翻译：用于产生至少第一和第二被乘数的乘积的乘法器电路包括包括多个编码器的编码电路。每个编码器操作以接收第一被乘数的比特的至少一个子集，并且生成对应于第一被乘数的比特的子集的部分乘积。编码电路还可操作以将产品的否定作为至少提供给乘法器电路的第一控制信号的函数。乘法器电路还包括与编码电路耦合的求和电路。求和电路用于对由编码电路产生的每个部分乘积进行求和，从而生成产品而不执行后递增。

15. 发明授权

US07296049B2 Fast multiplication circuits 失效
标题翻译：快速乘法电路
公开(公告)号：US07296049B2
公开(公告)日：2007-11-13
申请号：US10140284
申请日：2002-05-08
申请人： Erik Højsted
发明人： Erik Højsted
IPC分类号： G06F7/52
CPC分类号： G06F7/5336
摘要： Fast multiplication of two operands may be achieved by an interstitial product generator that generates an interstitial product from each of a plurality of mult-ibit segments of a multiplier. Generation of a final product is made faster because fewer interstitial products are created than in prior systems and, therefore, summing of the interstitial products is faster. In one embodiment, an interstitial product generator is used having registers to store a multiplicand value (“A”), shifted values of A and a 3A value. A series of multiplexers and an inverter may generate interstitial product values from data in these registers. This embodiment is useful with four bit segments of the multiplicand.
摘要翻译：两个操作数的快速乘法可以通过间隔产品生成器来实现，所述间隙产品生成器从乘法器的多个多单位段中的每一个生成间隔乘积。最终产品的生成更快，因为创建的间隙产品比以前的系统更少，因此，间隙产品的总和更快。在一个实施例中，使用具有用于存储被乘数值（“A”），移位值A和A A值的寄存器的间隙乘积产生器。一系列多路复用器和逆变器可以从这些寄存器中的数据生成间隙产品值。该实施例对被乘数的四位段是有用的。

16. 发明授权

US07177894B2 Switching activity reduced coding for low-power digital signal processing circuitry 失效
标题翻译：开关活动减少了低功耗数字信号处理电路的编码
公开(公告)号：US07177894B2
公开(公告)日：2007-02-13
申请号：US10650641
申请日：2003-08-28
申请人： Christian Lutkemeyer
发明人： Christian Lutkemeyer
IPC分类号： G06F7/52
CPC分类号： G06F7/533 , G06F7/5336 , H03H17/0236 , H03H2017/0692
摘要： A system and method for reducing power consumption in digital circuitry by reducing the amount of unnecessary switching in such circuitry. An aspect of the present invention provides a switching-reduction circuit that outputs a signal to a subsequent digital circuit. The value of the signal may depend on the relevance of the signal value to a next output of the subsequent digital circuit. A method according to various aspects of the present invention includes receiving a next input signal. The method further includes determining whether the next input signal may be relevant to a next output of a subsequent digital circuit. The method further includes providing the next input signal to the subsequent digital circuit when the next input signal may be relevant to the next output of the subsequent digital circuit, and providing a previous signal to the subsequent digital circuit when the next input signal will not be relevant to the next output of the subsequent digital circuit.
摘要翻译：一种通过减少这种电路中不必要的切换量来减少数字电路中的功耗的系统和方法。本发明的一个方面提供一种将信号输出到随后的数字电路的开关降低电路。信号的值可以取决于信号值与后续数字电路的下一个输出的相关性。根据本发明的各个方面的方法包括接收下一个输入信号。该方法还包括确定下一个输入信号是否可能与随后数字电路的下一个输出有关。该方法还包括当下一个输入信号可能与随后的数字电路的下一个输出相关时，向随后的数字电路提供下一个输入信号，并且当下一个输入信号不会与后续数字电路的下一个输出相关。

17. 发明授权

US06901423B1 Noise invariant circuits, systems and methods 有权
公开(公告)号：US06901423B1
公开(公告)日：2005-05-31
申请号：US09840530
申请日：2001-04-23
申请人： Edwin De Angel , Eric J. Swanson
发明人： Edwin De Angel , Eric J. Swanson
IPC分类号： G06F1/26 , G06F7/52 , G06F7/533 , G06J1/00
CPC分类号： G06F7/5336 , G06F2207/3868
摘要： The electrical circuitry for a multiplier system includes a counter for determining proximity to sampling operation, and a switch to select between symmetrical noise invariant operation and a low-power mode of operation. A noise invariant circuit disables row skip operation in a multi-row multiplier, to enable analog sampling. Disabling of the row skip operation is accomplished at a time which is several digital cycles preceding the time of analog sampling. Power saving multiplier row skippage resumes after analog sampling is completed.

18. 发明申请

US20030182343A1 Fast multiplication circuits 失效
标题翻译：快速乘法电路
公开(公告)号：US20030182343A1
公开(公告)日：2003-09-25
申请号：US10140284
申请日：2002-05-08
发明人： Erik Hojsted
IPC分类号： G06F007/52
CPC分类号： G06F7/5336
摘要： Fast multiplication of two operands may be achieved by an interstitial product generator that generates an interstitial product from each of a plurality of mult-ibit segments of a multiplier. Generation of a final product is made faster because fewer interstitial products are created than in prior systems and, therefore, summing of the interstitial products is faster. In one embodiment, an interstitial product generator is used having registers to store a multiplicand value (nullAnull), shifted values of A and a 3A value. A series of multiplexers and an inverter may generate interstitial product values from data in these registers. This embodiment is useful with four bit segments of the multiplicand.
摘要翻译：两个操作数的快速乘法可以通过间隔产品生成器来实现，所述间隙产品生成器从乘法器的多个多单位段中的每一个生成间隔乘积。最终产品的生成更快，因为创建的间隙产品比以前的系统更少，因此，间隙产品的总和更快。在一个实施例中，使用具有用于存储被乘数值（“A”），移位值A和3A值的寄存器的间隙乘积产生器。一系列多路复用器和逆变器可以从这些寄存器中的数据生成间隙产品值。该实施例对被乘数的四位段是有用的。

19. 发明授权

US5740094A Self-timed multiplier array 失效
标题翻译：自定时乘数数组
公开(公告)号：US5740094A
公开(公告)日：1998-04-14
申请号：US515335
申请日：1995-08-21
申请人： Peter Juergen Klim
发明人： Peter Juergen Klim
IPC分类号： G06F7/52
CPC分类号： G06F7/5336 , G06F2207/3884
摘要： Logic circuitry implemented in a pipeline manner receives a request signal along with received data into the pipeline and proceeds to insure that each successive stage within the pipeline is placed into a standby state and out of a precharge state previous to the arrival of the data wave into each of the successive stages. The circuitry also resets each of the stages after a stage has evaluated the data. The logic circuitry may be employed within a multiplier array in a processor.
摘要翻译：以流水线方式实现的逻辑电路将接收到的数据的请求信号接收到流水线中，并进行确保管线内的每个连续级被置于待机状态，并且在数据波到达之前的预充电状态每个连续阶段。在阶段评估数据之后，电路还重置每个阶段。逻辑电路可以在处理器中的乘法器阵列内使用。

20. 发明授权

US4745570A Binary multibit multiplier 失效
标题翻译：二进制多位乘法器
公开(公告)号：US4745570A
公开(公告)日：1988-05-17
申请号：US867167
申请日：1986-05-27
申请人： Richard A. Diedrich , Jay A. Lawrence
发明人： Richard A. Diedrich , Jay A. Lawrence
IPC分类号： G06F7/533 , G06F7/508 , G06F7/52 , G06F7/523
CPC分类号： G06F7/5336
摘要： A digital multiplier has recoders for recoding the multiplier bits to form selection bits which are applied to selectors for selecting forms of the multiplicand, either the multiplicand itself or multiples of the multiplicand, the selected forms being applied to adders which produce partial products, the adders being interconnected to produce the product. Special product generators simultaneously generate multiples of the multiplicand which are applied to the selectors.
摘要翻译：数字乘法器具有用于对乘法器位进行重新编码的编码器，以形成选择位，该选择位被应用于用于选择被乘数形式的选择器，被乘数本身或被乘数的倍数，所选择的形式被应用于产生部分积的加法器，加法器互连以产生产品。特殊产品发生器同时产生被施加到选择器的倍数。

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