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11. 发明申请

US20140125298A1 FAULT-REJECTING MIXER AND APPLICATIONS 审中-公开
标题翻译：故障排除混合器和应用
公开(公告)号：US20140125298A1
公开(公告)日：2014-05-08
申请号：US13669807
申请日：2012-11-06
申请人： VOLTERRA SEMICONDUCTOR CORPORATION
发明人： Patrice Lethellier
IPC分类号： H03D7/14 , G05F1/46
CPC分类号： G05F1/46 , H03D7/125 , H03D7/165 , H03D2200/0074
摘要： Mixers are described which allow for information sharing in redundant systems, while providing sufficient isolation between redundant system components to enable fault-tolerant operation.
摘要翻译：描述了混合器，其允许冗余系统中的信息共享，同时在冗余系统组件之间提供足够的隔离以实现容错操作。

12. 发明授权

US08710810B1 Systems and methods for DC-to-DC converter control 有权
标题翻译：用于DC-DC转换器控制的系统和方法
公开(公告)号：US08710810B1
公开(公告)日：2014-04-29
申请号：US13167674
申请日：2011-06-23
申请人： Michael D. McJimsey , David B. Lidsky , Andrew Burstein , Giovanni Garcea , Jeremy M. Flasck , Ilija Jergovic , Andrea Pizzutelli
发明人： Michael D. McJimsey , David B. Lidsky , Andrew Burstein , Giovanni Garcea , Jeremy M. Flasck , Ilija Jergovic , Andrea Pizzutelli
IPC分类号： H02M3/158 , H02M3/157
CPC分类号： H02M3/158 , H02M1/084 , H02M3/157 , H02M3/1584 , H02M2001/0003 , H03H7/20
摘要： A regulated, power supply system is described using multiphase DC-DC converters with dynamic fast-turnon, slow-turnoff phase shedding, early phase turn-on, and both load-voltage and drive-transistor feedback to pulsewidth modulators to provide fast response to load transients. In an embodiment, a system master can automatically determine whether all, or only some, slave phase units are fully populated. The programmable system includes fault detection with current and voltage sensing, telemetry capability, and automatic shutdown capability. In an embodiment, these are buck-type converters with or without coupled inductors, however some of the embodiments illustrated include boost configurations.
摘要翻译：使用具有动态快速旋转，慢关闭相位脱落，早期相位接通以及负载电压和驱动晶体管反馈到脉宽调制器的多相DC-DC转换器来描述稳压电源系统，以提供快速响应负载瞬变。在一个实施例中，系统主机可以自动地确定是否完全填充了所有或只有一些从动相位单元。可编程系统包括电流和电压检测，遥测能力和自动关机功能的故障检测。在一个实施例中，这些是具有或不具有耦合电感器的降压型转换器，然而所示实施例的一些包括升压配置。

13. 发明申请

US20140103894A1 Maximum Power Point Tracking Controllers And Associated Systems And Methods 有权
标题翻译：最大功率点跟踪控制器及相关系统和方法
公开(公告)号：US20140103894A1
公开(公告)日：2014-04-17
申请号：US13653381
申请日：2012-10-16
申请人： VOLTERRA SEMICONDUCTOR CORPORATION
发明人： Michael D. McJimsey , Anthony J. Stratakos , Ilija Jergovic , Xin Zhang , Kaiwei Yao , Vincent W. Ng , Phong T. Nguyen , Artin Der Minassians
IPC分类号： G05F1/46 , H03L5/00 , G06G7/16 , H03K5/00
CPC分类号： H02M3/158 , G01R21/06 , G05F1/67 , H02J3/385 , H03K3/356165 , Y02E10/58
摘要： A maximum power point tracking controller includes an input port for electrically coupling to an electric power source, an output port for electrically coupling to a load, a control switching device, and a control subsystem. The control switching device is adapted to repeatedly switch between its conductive and non-conductive states to transfer power from the input port to the output port. The control subsystem is adapted to control switching of the control switching device to regulate a voltage across the input port, based at least in part on a signal representing current flowing out of the output port, to maximize a signal representing power out of the output port.
摘要翻译：最大功率点跟踪控制器包括用于电耦合到电源的输入端口，用于电耦合到负载的输出端口，控制切换装置和控制子系统。控制切换装置适于在其导电状态和非导通状态之间重复切换，以将功率从输入端口传送到输出端口。控制子系统至少部分地基于表示从输出端口流出的电流的信号来控制控制切换装置的切换以调节输入端口上的电压，以最大化表示从输出端口输出的电力的信号。

14. 发明授权

US08553438B1 Voltage regulator with inductor banks 有权
标题翻译：带电感器组的稳压器
公开(公告)号：US08553438B1
公开(公告)日：2013-10-08
申请号：US13222574
申请日：2011-08-31
申请人： Aaron M. Schultz
发明人： Aaron M. Schultz
IPC分类号： H02M7/00
CPC分类号： H02M3/1584 , H02J3/1842 , Y02E40/22
摘要： A voltage regulator coupled to an unregulated DC input voltage source by an input terminal, and to a load by an output terminal is disclosed. The voltage regulator converts an input voltage at the input terminal to an output voltage at the output terminal. The voltage regulator includes one or more slaves, and each slave includes a switching circuit which serves as a power switch for alternately coupling and decoupling the input terminal to an intermediate node. The voltage regulator also includes a filter coupled to the slaves, the filter including one or more inductor banks each of which having a predetermined number of inductors.
摘要翻译：公开了一种通过输入端子耦合到未调节的DC输入电压源并由输出端子耦合到负载的稳压器。电压调节器将输入端的输入电压转换为输出端的输出电压。电压调节器包括一个或多个从器件，并且每个从器件包括切换电路，其用作用于将输入端子交替耦合和去耦合到中间节点的功率开关。电压调节器还包括耦合到从器件的滤波器，滤波器包括一个或多个电感器组，每个电感器具有预定数量的电感器。

15. 发明授权

US08487604B2 Asymmetrical coupled inductors and associated methods 有权
标题翻译：非对称耦合电感器及相关方法
公开(公告)号：US08487604B2
公开(公告)日：2013-07-16
申请号：US13709778
申请日：2012-12-10
申请人： Volterra Semiconductor Corporation
发明人： Alexandr Ikriannikov , Ognjen Djekic
IPC分类号： H02M3/10
CPC分类号： G05F1/46 , H01F3/10 , H01F3/14 , H01F38/023 , H02M3/1584 , H02M2001/0032 , Y02B70/16
摘要： An asymmetrical coupled inductor includes a first and a second winding and a core. The core is formed of a magnetic material and magnetically couples together the windings. The core is configured such that a leakage inductance value of the first winding is greater than a leakage inductance value of the second winding. The coupled inductor is included, for example, in a multi-phase DC-to-DC converter. A DC-to-DC converter including a symmetrical coupled inductor includes at least one additional inductor electrically coupled in series with one or more of the coupled inductor's windings. A controller for a DC-to-DC converter including a first phase having an effective inductance value greater than an effective inductance value of a second phase is configured to shut down the second phase while the first phase remains operational during a light load operating condition.
摘要翻译：非对称耦合电感器包括第一和第二绕组和芯。芯由磁性材料形成，并将绕组磁耦合在一起。芯体被配置为使得第一绕组的漏电感值大于第二绕组的漏电感值。耦合电感器例如包括在多相DC-DC转换器中。包括对称耦合电感器的DC-DC转换器包括与一个或多个耦合电感器绕组串联电耦合的至少一个附加电感器。包括具有大于第二相的有效电感值的有效电感值的第一相的DC-DC转换器的控制器被配置为在第一阶段在轻负载操作条件期间保持工作时关闭第二相。

16. 发明申请

US20130154589A1 DC TO DC CONVERTER DESIGNED TO MITIGATE PROBLEMS ASSOCIATED WITH LOW DUTY CYCLE OPERATION 有权
标题翻译： DC-DC转换器设计用于减少与低周期运行相关的问题
公开(公告)号：US20130154589A1
公开(公告)日：2013-06-20
申请号：US13325562
申请日：2011-12-14
申请人： Patrice Lethellier
发明人： Patrice Lethellier
IPC分类号： G05F1/46
CPC分类号： H02M3/155 , H02M1/44 , H02M3/158 , H02M2003/1586
摘要： DC to DC converters are described that include two converters interconnected and operated to mitigate at least some of the effects of low duty cycle operation.
摘要翻译：描述了DC至DC转换器，其包括互连和操作的两个转换器以减轻低占空比操作的至少一些影响。

17. 发明申请

US20130109143A1 Vertical Gate LDMOS Device 有权
标题翻译：垂直门LDMOS器件
公开(公告)号：US20130109143A1
公开(公告)日：2013-05-02
申请号：US13572281
申请日：2012-08-10
申请人： Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan , John Xia
发明人： Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan , John Xia
IPC分类号： H01L29/78
CPC分类号： H01L29/66704 , H01L21/265 , H01L21/28105 , H01L21/823481 , H01L27/088 , H01L29/0626 , H01L29/063 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66696 , H01L29/78 , H01L29/7802 , H01L29/7825 , H01L29/7827 , H01L29/7835
摘要： The present application features methods of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor. In one aspect, a method includes depositing a masking layer on an n-well region implanted on a substrate, patterning the masking layer to define an area, and forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region. The method also includes filling the first trench by a conductive material and depositing a layer of oxide over the area. The method further includes etching out at least a portion of the oxide layer to expose a portion of the conductive material, removing the conductive material from the exposed portion to form a second trench, and filling the second trench with an oxide to form an asymmetric gate of the transistor.
摘要翻译：本申请的特征在于在垂直横向扩散的金属氧化物半导体（LDMOS）晶体管中制造栅极区域的方法。在一个方面，一种方法包括在植入在衬底上的n阱区域上沉积掩模层，图案化掩模层以限定区域，以及在该区域中形成第一沟槽，使得第一沟槽的长度从 n阱区域的表面到n阱区域中的第一深度。该方法还包括通过导电材料填充第一沟槽并在该区域上沉积一层氧化物。该方法还包括蚀刻掉氧化物层的至少一部分以暴露导电材料的一部分，从暴露部分去除导电材料以形成第二沟槽，并用氧化物填充第二沟槽以形成非对称栅极的晶体管。

18. 发明授权

US08405148B1 Method of fabricating a lateral double-diffused MOSFET (LDMOS) transistor and a conventional CMOS transistor 有权
公开(公告)号：US08405148B1
公开(公告)日：2013-03-26
申请号：US13185356
申请日：2011-07-18
申请人： Budong You , Marco A. Zuniga
发明人： Budong You , Marco A. Zuniga
IPC分类号： H01L29/66
CPC分类号： H01L29/7816 , H01L21/823814 , H01L21/823857 , H01L21/8249 , H01L27/0623 , H01L27/0922 , H01L29/0847 , H01L29/086 , H01L29/0878 , H01L29/66674 , H01L29/7801 , H01L29/7824
摘要： An integrated circuit structure having an LDMOS transistor and a CMOS transistor includes a p-type substrate having a surface, an n-well implanted in the substrate, the first n-well providing a CMOS n-well, a CMOS transistor including a CMOS source with a first p+ region implanted in the n-well, a CMOS drain with a second p+ region implanted in the n-well, and a CMOS gate between the first p+ region and the second p+ region, and an LDMOS transistor including an LDMOS source with an LDMOS source including a p-body implanted in the n-well, a third p+ region implanted in the p-body, and a first n+ region implanted in the p-body, an LDMOS drain including an n-doped shallow drain implanted in the n-well, and a second n+ region implanted in the n-doped shallow drain, and an LDMOS gate between the third p+ region and the second n+ region.

19. 发明授权

US08368212B1 Semiconductor package with under bump metallization routing 有权
标题翻译：半导体封装，具有凹凸金属化布线
公开(公告)号：US08368212B1
公开(公告)日：2013-02-05
申请号：US13192303
申请日：2011-07-27
申请人： Ilija Jergovic , Efren M. Lacap
发明人： Ilija Jergovic , Efren M. Lacap
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/492 , H01L23/4824 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/0346 , H01L2224/03462 , H01L2224/0401 , H01L2224/05012 , H01L2224/05027 , H01L2224/05083 , H01L2224/05096 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05541 , H01L2224/05552 , H01L2224/05647 , H01L2224/11444 , H01L2224/1147 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/81191 , H01L2224/81815 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor package includes a semiconductor substrate a semiconductor substrate having source and drain regions formed therein, an intermediate routing structure to provide electrical interconnects to the source and drain regions, a dielectric layer formed over the intermediate routing structure, and an under-bump-metallization (UBM) stack. The intermediate routing structure includes an outermost conductive layer, and the dielectric layer has an opening positioned over a portion of the intermediate layer routing structure. The UBM stack includes a conductive base layer formed over the dielectric layer and electrically connected to the outermost conductive layer through the opening, and a thick conductive layer formed on the base layer. A conductive bump is positioned on the UBM stack and laterally spaced from the opening.
摘要翻译：半导体封装包括半导体衬底，其中形成有源极和漏极区域的半导体衬底，用于向源极和漏极区域提供电互连的中间布线结构，在中间布线结构上形成的介电层，以及凹凸下金属化（UBM）堆栈。中间布线结构包括最外面的导电层，并且介电层具有位于中间层布线结构的一部分上的开口。 UBM堆叠包括形成在电介质层上并且通过开口电连接到最外面的导电层的导电基底层，以及形成在基底层上的厚的导电层。导电凸块定位在UBM堆叠上并且与开口横向间隔开。

20. 发明授权

US08350658B1 Method for making magnetic components with N-phase coupling, and related inductor structures 有权
公开(公告)号：US08350658B1
公开(公告)日：2013-01-08
申请号：US12987944
申请日：2011-01-10
申请人： Anthony Stratakos , Charles R. Sullivan , Jieli Li
发明人： Anthony Stratakos , Charles R. Sullivan , Jieli Li
IPC分类号： H01F27/24
CPC分类号： H01F3/00 , H01F3/10 , H01F17/0006 , H01F17/06 , H01F30/12 , H01F2017/067 , H02M7/003 , H02M2001/0064
摘要： Methods and structures for constructing a magnetic core of a coupled inductor. The method provides for constructing N-phase coupled inductors as both single and scalable magnetic structures, where N is an integer greater than 1. The method additionally describes how such a construction of the magnetic core may enhance the benefits of using the scalable N-phase coupled inductor. The first and second magnetic cores may be formed into shapes that, when coupled together, may form a single scalable magnetic core. For example, the cores can be fashioned into shapes such as a U, an I, an H, a ring, a rectangle, and a comb, that cooperatively form the single magnetic core.

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