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11. 发明申请

US20130334604A1 SOI SEMICONDUCTOR DEVICE COMPRISING A SUBSTRATE DIODE AND A FILM DIODE FORMED BY USING A COMMON WELL IMPLANTATION MASK 审中-公开
标题翻译：包含基板二极管的SOI半导体器件和使用通用的植入掩膜形成的膜二极管
公开(公告)号：US20130334604A1
公开(公告)日：2013-12-19
申请号：US13968545
申请日：2013-08-16
申请人： GLOBAL FOUNDRIES Inc.
发明人： Thilo Scheiper , Stefan Flachowsky
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L27/1207
摘要： When forming sophisticated SOI devices, a substrate diode and a film diode are formed by using one and the same implantation mask for determining the well dopant concentration in the corresponding well regions. Consequently, during the further processing, the well dopant concentration of any transistor elements may be achieved independently from the well regions of the diode in the semiconductor layer.
摘要翻译：当形成复杂的SOI器件时，通过使用一个相同的注入掩模来形成衬底二极管和膜二极管，以确定相应阱区中的阱掺杂剂浓度。因此，在进一步处理期间，可以独立于半导体层中的二极管的阱区实现任何晶体管元件的阱掺杂剂浓度。

12. 发明授权

US08482084B2 SOI schottky source/drain device structure to control encroachment and delamination of silicide 失效
标题翻译： SOI肖特基源/漏极器件结构，以控制硅化物的侵蚀和分层
公开(公告)号：US08482084B2
公开(公告)日：2013-07-09
申请号：US12726789
申请日：2010-03-18
申请人： Marwan H. Khater , Christian Lavoie , Bin Yang , Zhen Zhang
发明人： Marwan H. Khater , Christian Lavoie , Bin Yang , Zhen Zhang
IPC分类号： H01L29/76 , H01L31/00
CPC分类号： H01L29/78654 , H01L29/7839
摘要： A Schottky field effect transistor is provided that includes a substrate having a layer of semiconductor material atop a dielectric layer, wherein the layer of semiconductor material has a thickness of less than 10.0 nm. A gate structure is present on the layer of semiconductor material. Raised source and drain regions comprised of a metal semiconductor alloy are present on the layer of semiconductor material on opposing sides of the gate structure. The raised source and drain regions are Schottky source and drain regions. In one embodiment, a first portion of the Schottky source and drain regions that is adjacent to a channel region of the Schottky field effect transistor contacts the dielectric layer, and a non-reacted semiconductor material is present between a second portion of the Schottky source and drain regions and the dielectric layer.
摘要翻译：提供一种肖特基场效应晶体管，其包括在电介质层顶上具有半导体材料层的衬底，其中半导体材料层的厚度小于10.0nm。栅极结构存在于半导体材料层上。在栅极结构的相对侧的半导体材料层上存在由金属半导体合金构成的凸起的源极和漏极区域。凸起的源极和漏极区域是肖特基源极和漏极区域。在一个实施例中，与肖特基场效应晶体管的沟道区相邻的肖特基源极和漏极区的第一部分接触电介质层，并且未反应的半导体材料存在于肖特基源的第二部分和漏区和电介质层。

13. 发明授权

US10622457B2 Forming replacement low-K spacer in tight pitch fin field effect transistors 有权
公开(公告)号：US10622457B2
公开(公告)日：2020-04-14
申请号：US14879968
申请日：2015-10-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES INC. , STMicroelectronics, Inc.
发明人： Xiuyu Cai , Chun-Chen Yeh , Qing Liu , Ruilong Xie
IPC分类号： H01L21/768 , H01L29/78 , H01L29/66 , H01L29/417 , H01L29/06 , H01L29/08 , H01L29/161 , H01L29/165
CPC分类号： H01L29/6656 , H01L21/76829 , H01L21/76897 , H01L29/0653 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/41775 , H01L29/41791 , H01L29/6653 , H01L29/66515 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7848 , H01L29/7851
摘要： A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.

14. 发明申请

US20170200698A1 THREE-DIMENSIONAL HYBRID PACKAGING WITH THROUGH-SILICON-VIAS AND TAPE-AUTOMATED-BONDING 有权
公开(公告)号：US20170200698A1
公开(公告)日：2017-07-13
申请号：US14994289
申请日：2016-01-13
申请人： Global Foundries Inc.
发明人： Richard S. Graf , Sebastian T. Ventrone
IPC分类号： H01L25/065 , H01L25/00
CPC分类号： H01L25/0657 , H01L23/48 , H01L23/482 , H01L23/495 , H01L24/50 , H01L25/00 , H01L25/065 , H01L25/50 , H01L29/40 , H01L29/41 , H01L2224/13025 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2224/50 , H01L2224/73261 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06579 , H01L2924/15311
摘要： A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.

15. 发明授权

US09448807B2 Automatic creation, deployment, and upgrade of disk images 有权
标题翻译：自动创建，部署和升级磁盘映像
公开(公告)号：US09448807B2
公开(公告)日：2016-09-20
申请号：US13872404
申请日：2013-04-29
申请人： GLOBALFOUNDRIES INC.
发明人： Walter Haug , Steffen Hees , Roland Seiffert , Stefan Letz , Jan-Bernd Themann
IPC分类号： G06F9/44 , G06F9/445
CPC分类号： G06F9/4401 , G06F8/63
摘要： A computer installs an operating system. The computer receives, in a logical partition (LPAR) via a management network, a deploy program configured to download a disk image from an image repository and to write the disk image to a first direct access storage device (DASD) of the LPAR. The disk image includes an operating system, applications, and management components including an upgrade program. The computer receives, in the LPAR via a data network, the disk image, and writes, to the first DASD of the LPAR, the disk image. The computer boots the LPAR into the operating system of the disk image written to the first DASD, and determines whether the installed operating system is a deployment or an upgrade.
摘要翻译：计算机安装操作系统。计算机经由管理网络在逻辑分区（LPAR）中接收配置为从图像存储库下载磁盘映像并将磁盘映像写入到LPAR的第一直接存取存储设备（DASD）的部署程序。磁盘映像包括操作系统，应用程序和管理组件，包括升级程序。计算机通过数据网络在LPAR中接收磁盘映像，并将其写入LPAR的第一个DASD，即磁盘映像。计算机将LPAR引导到写入第一个DASD的磁盘映像的操作系统中，并确定安装的操作系统是部署还是升级。

16. 发明授权

US09129987B2 Replacement low-K spacer 有权
标题翻译：替换低K隔片
公开(公告)号：US09129987B2
公开(公告)日：2015-09-08
申请号：US14163687
申请日：2014-01-24
申请人： GLOBALFOUNDRIES Inc.
发明人： Jing Wan , Jin Ping Liu , Guillaume Bouche , Andy Wei , Lakshmanan H. Vanamurthy , Cuiqin Xu , Sridhar Kuchibhatla , Rama Kambhampati , Xiuyu Cai
IPC分类号： H01L29/66 , H01L21/3105 , H01L21/311 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/28079 , H01L21/28088 , H01L21/31055 , H01L21/31111 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A method includes providing a gate structure having a gate, a first spacer along at least one side of the gate and an interlayer dielectric on at least one of the gate and the first spacer. The interlayer dielectric is removed to reveal the first spacer. The first spacer is removed and a second spacer is deposited on at least one side of the gate. The second spacer is formed of material having a lower dielectric constant than the first spacer.
摘要翻译：一种方法包括提供具有栅极的栅极结构，沿栅极的至少一侧的第一间隔物，以及至少一个栅极和第一间隔物上的层间电介质。去除层间电介质以露出第一间隔物。去除第一间隔物并且在栅极的至少一侧上沉积第二间隔物。第二间隔物由具有比第一间隔物低的介电常数的材料形成。

17. 发明申请

US20150214219A1 GATE STRUCTURE CUT AFTER FORMATION OF EPITAXIAL ACTIVE REGIONS 有权
标题翻译：形成外来活动区域后的门结构切割
公开(公告)号：US20150214219A1
公开(公告)日：2015-07-30
申请号：US14162904
申请日：2014-01-24
申请人： GLOBAL FOUNDRIES INC. , INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Xiuyu Cai , Kangguo Cheng , Johnathan E. Faltermeier , Ali Khakifirooz , Theodorus E. Standaert , Ruilong Xie
IPC分类号： H01L27/088 , H01L29/08 , H01L29/66 , H01L21/8234
CPC分类号： H01L21/823437 , H01L21/31111 , H01L21/823418 , H01L21/823431 , H01L21/823468 , H01L21/845 , H01L27/088 , H01L27/0886 , H01L29/0847 , H01L29/41783 , H01L29/665 , H01L29/66795 , H01L29/785
摘要： A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.
摘要翻译：形成跨越多个半导体材料部分的栅极结构。源极区域和漏极区域形成在多个半导体材料部分中，并且形成横向围绕栅极结构的栅极间隔物。通过选择性外延工艺从源极和漏极区域形成外延有源区。通过切割掩模和蚀刻将栅极结构和栅极间隔物的组装切成多个部分以形成多个栅极组件。每个门组件包括栅极结构部分和由栅极结构部分横向隔开的两个分离的栅极间隔部分。可以从栅极间隔物的侧壁的周围去除外延有源区的一部分，以防止外延有源区中的电短路。可以使用电介质间隔物或电介质衬垫来限制形成金属半导体合金的区域。

18. 发明申请

US20150194350A1 THRESHOLD VOLTAGE TUNING USING SELF-ALIGNED CONTACT CAP 有权
标题翻译：使用自对准触点盖的电压调节
公开(公告)号：US20150194350A1
公开(公告)日：2015-07-09
申请号：US14147108
申请日：2014-01-03
申请人： GLOBAL FOUNDRIES Inc.
发明人： Xiuyu Harry CAI , Chanro PARK , Hoon KIM
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/423 , H01L21/28
CPC分类号： H01L21/823828 , H01L21/0217 , H01L21/022 , H01L21/28176 , H01L21/8238 , H01L21/823821 , H01L21/823857 , H01L27/092 , H01L29/66545
摘要： Methods of forming a PFET dielectric cap with varying concentrations of H2 reactive gas and the resulting devices are disclosed. Embodiments include forming p-type and n-type metal gate stacks, each surrounded by SiN spacers; forming an ILD surrounding the SiN spacers; planarizing the ILD, the metal gate stacks, and the SiN spacers; determining at least one desired threshold voltage for the p-type metal gate stack; forming a first cavity in the p-type metal gate stack for each desired threshold voltage and a second cavity in the n-type metal gate stack; selecting a first nitride layer for each first cavity, the first nitride layer for each cavity having a concentration of hydrogen reactive gas based on the desired threshold voltage associated with the cavity; forming the first nitride layers in the respective first cavities; and forming a second nitride layer, with a hydrogen rich reactive gas, in the second cavity.
摘要翻译：公开了形成具有不同浓度的H 2反应气体的PFET电介质盖的方法和所得到的装置。实施例包括形成p型和n型金属栅叠层，每一个被SiN间隔物环绕; 形成围绕SiN间隔物的ILD; 平面化ILD，金属栅极堆叠和SiN间隔物; 确定p型金属栅极堆叠的至少一个期望的阈值电压; 在所述p型金属栅极堆叠中形成每个所需阈值电压的第一空腔和所述n型金属栅极叠层中的第二空腔; 为每个第一空腔选择第一氮化物层，基于与空腔相关联的期望阈值电压，每个空腔的第一氮化物层具有氢反应性气体的浓度; 在相应的第一空腔中形成第一氮化物层; 以及在所述第二腔中形成具有富氢反应性气体的第二氮化物层。

19. 发明申请

US20150171216A1 METHODS OF FORMING REPLACEMENT GATE STRUCTURES FOR SEMICONDUCTOR DEVICES AND THE RESULTING SEMICONDUCTOR PRODUCTS 有权
标题翻译：形成半导体器件和半导体器件产品替代门结构的方法
公开(公告)号：US20150171216A1
公开(公告)日：2015-06-18
申请号：US14107279
申请日：2013-12-16
申请人： GLOBAL FOUNDRIES Inc.
发明人： Ruilong Xie , Xiuyu Cai , Andy C. Wei
IPC分类号： H01L29/78 , H01L21/311 , H01L21/28 , H01L29/66 , H01L21/02
CPC分类号： H01L29/7856 , H01L21/02164 , H01L21/0217 , H01L21/28035 , H01L21/31111 , H01L29/0649 , H01L29/66545 , H01L29/66795 , H01L29/7851
摘要： One method disclosed includes, forming a sacrificial gate structure trench in a stack of sacrificial material layers, forming a sacrificial gate structure within the trench, performing at least one process operation to remove at least portions of the stack of sacrificial material layers and thereby expose sidewalls of the sacrificial gate structure, forming a sidewall spacer adjacent the exposed sidewalls of the sacrificial gate structure, removing the sacrificial gate structure so as to define a replacement gate cavity between the spacers, forming a replacement gate structure in the replacement gate cavity, and forming a gate cap above the replacement gate structure within the replacement gate cavity.
摘要翻译：所公开的一种方法包括：在牺牲材料层的堆叠中形成牺牲栅极结构沟槽，在沟槽内形成牺牲栅极结构，执行至少一个处理操作以移除堆叠的牺牲材料层的至少一部分，从而暴露侧壁形成邻近牺牲栅极结构的暴露的侧壁的侧壁间隔物，去除牺牲栅极结构，以在间隔物之间限定替换栅极腔，在置换栅腔中形成替代栅极结构，并形成位于置换门腔内的替换栅极结构上方的栅极盖。

20. 发明申请

US20150140477A1 EUV MASK FOR USE DURING EUV PHOTOLITHOGRAPHY PROCESSES 有权
标题翻译： EUV光刻过程中使用的EUV掩模
公开(公告)号：US20150140477A1
公开(公告)日：2015-05-21
申请号：US14080939
申请日：2013-11-15
申请人： GLOBAL FOUNDRIES Inc.
发明人： Mandeep Singh
IPC分类号： G03F1/24 , G03F7/20 , G03F1/48
CPC分类号： G03F7/20 , G03F1/24 , G03F1/48 , G03F7/2002 , G03F7/2004
摘要： The present disclosure is directed to various masks for use during EUV photolithography processes. In one example, an EUV mask is disclosed that includes, among other things, a substrate, a multilayer stack comprised of a plurality of multilayer pairs of ruthenium and silicon formed above the substrate, wherein the mask is adapted to, when irradiated with EUV light, have an effective reflective plane that is positioned 32 nm or less below an uppermost surface of the multilayer stack and a capping layer positioned above the uppermost surface of the multilayer stack.
摘要翻译：本公开涉及在EUV光刻工艺期间使用的各种掩模。在一个示例中，公开了一种EUV掩模，其包括衬底，由在衬底上形成的多个多层钌和硅组成的多层堆叠，其中所述掩模适于当用EUV光照射时具有位于多层堆叠的最上表面下方32nm或更小的有效反射平面以及位于多层堆叠的最上表面之上的覆盖层。

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