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11. 发明授权

US08062800B2 Catalyst for reformer used in fuel cell system, reformer, and fuel cell system comprising same 有权
标题翻译：用于燃料电池系统，重整器和包含燃料电池系统的燃料电池系统中的重整器的催化剂
公开(公告)号：US08062800B2
公开(公告)日：2011-11-22
申请号：US11490203
申请日：2006-07-21
申请人： Eun-Suk Cho , Zin Park , In-Hyuk Son , Dong-Myung Suh
发明人： Eun-Suk Cho , Zin Park , In-Hyuk Son , Dong-Myung Suh
IPC分类号： H01M8/00 , H01M8/04 , H01M8/06
CPC分类号： B01J23/44 , B01J21/04 , B01J23/42 , B01J35/023 , C01B3/326 , C01B2203/0233 , C01B2203/0283 , C01B2203/066 , C01B2203/0811 , C01B2203/1011 , C01B2203/1041 , C01B2203/1047 , C01B2203/1058 , C01B2203/107 , C01B2203/1076 , C01B2203/1082 , C01B2203/1223 , C01B2203/1229 , C01B2203/1288 , H01M8/04014 , H01M8/04059 , H01M8/0618 , Y02P20/52
摘要： A catalyst for a reformer of a fuel cell system, a reformer for a fuel cell system including the catalyst, and a fuel cell system including the reformer are provided. The reformer includes a first reacting region that generates heat energy through oxidation of fuel and includes an oxidation catalyst having a Pd catalyst supported by an Al2O3 carrier and a Pt catalyst supported by an Al2O3 carrier, and a second reacting region that generates hydrogen gas from the fuel through a reforming reaction by the heat energy. The reformer includes at least two pipes each having an independent internal space and letting the fuel containing hydrogen pass therethrough.
摘要翻译：提供了一种用于燃料电池系统的重整器的催化剂，包括该催化剂的燃料电池系统的重整器和包括该重整器的燃料电池系统。重整器包括通过燃料氧化产生热能的第一反应区域，并且包括具有由Al 2 O 3载体负载的Pd催化剂和由Al 2 O 3载体负载的Pt催化剂的氧化催化剂和从所述Al 2 O 3载体产生氢气的第二反应区域燃料通过热能的重整反应。重整器包括至少两个管，每个管具有独立的内部空间，并使含有氢的燃料通过。

12. 发明授权

US07473611B2 Methods of forming non-volatile memory cells including fin structures 失效
标题翻译：形成包括鳍结构的非易失性存储单元的方法
公开(公告)号：US07473611B2
公开(公告)日：2009-01-06
申请号：US10975643
申请日：2004-10-28
申请人： Eun-Suk Cho , Choong-Ho Lee , Tae-Yong Kim
发明人： Eun-Suk Cho , Choong-Ho Lee , Tae-Yong Kim
IPC分类号： H01L21/20
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42316 , H01L29/42324 , H01L29/7851 , H01L29/7854 , H01L29/792
摘要： A method of forming a non-volatile memory device may include forming a fin protruding from a substrate, forming a tunnel insulating layer on portions of the fin, and forming a floating gate on the tunnel insulting layer so that the tunnel insulating layer is between the floating gate and the fin. A dielectric layer may be formed on the floating gate so that the floating gate is between the dielectric layer and the fin, and a control gate electrode may be formed on the dielectric layer so that the dielectric layer is between the control gate and the fin. Related devices are also discussed.
摘要翻译：形成非易失性存储器件的方法可以包括形成从衬底突出的翅片，在鳍的部分上形成隧道绝缘层，并且在隧道绝缘层上形成浮栅，使得隧道绝缘层在浮动门和鳍。可以在浮置栅极上形成电介质层，使得浮置栅极位于电介质层和鳍之间，并且可以在电介质层上形成控制栅电极，使得电介质层位于控制栅和鳍之间。还讨论了相关设备。

13. 发明申请

US20080303079A1 Non-volatile Memory Cells Including Fin Structures 失效
标题翻译：包括鳍结构的非易失性存储单元
公开(公告)号：US20080303079A1
公开(公告)日：2008-12-11
申请号：US12193200
申请日：2008-08-18
申请人： Eun-Suk Cho , Choong-Ho Lee , Tae-Yong Kim
发明人： Eun-Suk Cho , Choong-Ho Lee , Tae-Yong Kim
IPC分类号： H01L29/00
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42316 , H01L29/42324 , H01L29/7851 , H01L29/7854 , H01L29/792
摘要： A method of forming a non-volatile memory device may include forming a fin protruding from a substrate, forming a tunnel insulating layer on portions of the fin, and forming a floating gate on the tunnel insulting layer so that the tunnel insulating layer is between the floating gate and the fin. A dielectric layer may be formed on the floating gate so that the floating gate is between the dielectric layer and the fin, and a control gate electrode may be formed on the dielectric layer so that the dielectric layer is between the control gate and the fin. Related devices are also discussed.
摘要翻译：形成非易失性存储器件的方法可以包括形成从衬底突出的翅片，在鳍的部分上形成隧道绝缘层，并且在隧道绝缘层上形成浮栅，使得隧道绝缘层在浮动门和鳍。可以在浮置栅极上形成电介质层，使得浮置栅极位于电介质层和鳍之间，并且可以在电介质层上形成控制栅电极，使得电介质层位于控制栅和鳍之间。还讨论了相关设备。

14. 发明授权

US07371638B2 Nonvolatile memory cells having high control gate coupling ratios using grooved floating gates and methods of forming same 失效
标题翻译：具有使用沟槽浮动栅极的高控制栅极耦合比的非易失性存储单元及其形成方法
公开(公告)号：US07371638B2
公开(公告)日：2008-05-13
申请号：US11121887
申请日：2005-05-04
申请人： Eun-Suk Cho , Choong-Ho Lee , Tae-Yong Kim
发明人： Eun-Suk Cho , Choong-Ho Lee , Tae-Yong Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/28282 , H01L29/42324 , H01L29/66787 , H01L29/7851 , H01L29/7853 , H01L29/7881
摘要： A non-volatile memory cell includes a semiconductor substrate having a fin-shaped active region extending therefrom. A tunnel dielectric layer is provided, which extends on opposing sidewalls and an upper surface of the fin-shaped active region. A floating gate electrode is provided on the tunnel dielectric layer. This floating gate electrode has at least a partial groove therein. An inter-gate dielectric layer is also provided. This inter-gate dielectric layer extends on the floating gate electrode and into the at least a partial groove. A control gate electrode is provided, which extends on the inter-gate dielectric layer and into the at least a partial groove.
摘要翻译：非易失性存储单元包括具有从其延伸的鳍状有源区的半导体衬底。提供隧道电介质层，其在相对的侧壁上延伸并且在鳍状有源区域的上表面上延伸。在隧道电介质层上设置浮栅电极。该浮栅电极中至少有一部分凹槽。还提供了栅极间电介质层。该栅极间电介质层在浮栅电极上延伸并进入至少一部分槽。提供控制栅极电极，其在栅极间电介质层上延伸并且进入至少部分凹槽。

15. 发明申请

US20110250747A1 MEMORY DEVICE AND METHOD FOR MANUFACTURING MEMORY DEVICES 失效
标题翻译：用于制造存储器件的存储器件和方法
公开(公告)号：US20110250747A1
公开(公告)日：2011-10-13
申请号：US13081849
申请日：2011-04-07
申请人： Suk-Joon Son , Eun-Suk Cho
发明人： Suk-Joon Son , Eun-Suk Cho
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L21/0206 , H01L21/02071 , H01L27/11521
摘要： Provided are a method for manufacturing a memory device and a memory device manufactured by the method. The memory device may be a flash memory device. The method for manufacturing the memory device may include sequentially stacking a tunnel dielectric, a floating gate conductive layer, an inter-gate dielectric, and a control gate conductive layer on a semiconductor substrate; anisotropically etching the floating gate conductive layer, the inter-gate dielectric, and the control gate conductive layer to form gate structures. The gate structures may be separated by regions where top surfaces of the tunnel dielectric are exposed, the exposed top surfaces being damaged during formation of the gate structures. The method includes reacting the exposed top surfaces of the tunnel dielectric damaged during the formation of the gate structures with a reaction gas comprising ammonium fluoride to form a reaction by-product on the exposed top surfaces of the tunnel dielectric, and removing the reaction by-product.
摘要翻译：提供一种用于制造通过该方法制造的存储器件和存储器件的方法。存储器件可以是闪存器件。用于制造存储器件的方法可以包括在半导体衬底上依次层叠隧道电介质，浮栅导电层，栅极间电介质和控制栅导电层; 各向异性蚀刻浮栅导电层，栅极间电介质和控制栅极导电层以形成栅极结构。栅极结构可以由隧道电介质的顶表面暴露的区域分开，暴露的顶表面在栅极结构的形成期间被损坏。该方法包括使形成栅极结构期间损坏的隧道电介质的暴露的顶表面与包含氟化铵的反应气体反应，以在隧道电介质的暴露的顶表面上形成反应副产物，产品。

16. 发明授权

US07419859B2 Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions 有权
标题翻译：制造具有对应于一对鳍型沟道区的单个栅电极的半导体器件的方法
公开(公告)号：US07419859B2
公开(公告)日：2008-09-02
申请号：US11505335
申请日：2006-08-17
申请人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
发明人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
IPC分类号： H01L21/84 , H01L29/94
CPC分类号： H01L29/785 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/10873 , H01L27/10879 , H01L27/1159 , H01L27/2436 , H01L29/66795
摘要： Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.
摘要翻译：提供了制造具有提供体偏置控制的鳍式FET结构的半导体器件的方法，显示出与SOI结构相关的一些特征优点，提供增加的工作电流和/或降低的接触电阻。制造半导体器件的方法包括在第一绝缘膜的突出部分的侧壁上形成绝缘间隔物; 通过使用绝缘间隔物作为蚀刻掩模去除半导体衬底的暴露区域，从而形成与第一绝缘膜接触并由第一绝缘膜支撑的鳍形成第二沟槽。在形成翅片之后，形成第三绝缘膜以填充第二沟槽并支撑翅片。然后去除第一绝缘膜的一部分以打开翅片之间的空间，其中可以形成包括栅极电介质，栅电极和附加接触，绝缘和存储节点结构的附加结构。

17. 发明申请

US20080001209A1 Non-volatile memory device and method of manufacturing the non-volatile memory device 审中-公开
标题翻译：非易失性存储器件和制造非易失性存储器件的方法
公开(公告)号：US20080001209A1
公开(公告)日：2008-01-03
申请号：US11783548
申请日：2007-04-10
申请人： Eun-Suk Cho , Kyu-Charn Park , Jong-Jin Lee , Jeong-Dong Choe
发明人： Eun-Suk Cho , Kyu-Charn Park , Jong-Jin Lee , Jeong-Dong Choe
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7883 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42336
摘要： A non-volatile memory device may include a substrate having a field region and an active region including a rounded upper edge portion and a flat upper central portion, an effective tunnel oxide layer on the flat upper central portion of the active region, a split floating gate electrode on the effective tunnel oxide layer, the floating gate electrode having a width greater than a width of the effective tunnel oxide layer, a dielectric layer pattern on the floating gate electrode, the dielectric layer pattern including metal oxide, and a control gate electrode on the dielectric layer pattern.
摘要翻译：非易失性存储器件可以包括具有场区域和包括圆形上边缘部分和平坦上中心部分的有源区域的基板，在有源区域的平坦上中心部分上的有效隧道氧化物层，分裂浮动栅极电极在有效隧道氧化物层上，浮栅电极的宽度大于有效隧道氧化物层的宽度，浮栅电极上的电介质层图案，包括金属氧化物的电介质层图案和控制栅电极在电介质层图案上。

18. 发明申请

US20070048934A1 Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions 有权
标题翻译：制造具有对应于一对鳍型沟道区的单个栅电极的半导体器件的方法
公开(公告)号：US20070048934A1
公开(公告)日：2007-03-01
申请号：US11505335
申请日：2006-08-17
申请人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
发明人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
IPC分类号： H01L21/8242
CPC分类号： H01L29/785 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/10873 , H01L27/10879 , H01L27/1159 , H01L27/2436 , H01L29/66795
摘要： Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.
摘要翻译：提供了制造具有提供体偏置控制的鳍式FET结构的半导体器件的方法，显示出与SOI结构相关的一些特征优点，提供增加的工作电流和/或降低的接触电阻。制造半导体器件的方法包括在第一绝缘膜的突出部分的侧壁上形成绝缘间隔物; 通过使用绝缘间隔物作为蚀刻掩模去除半导体衬底的暴露区域，从而形成与第一绝缘膜接触并由第一绝缘膜支撑的鳍形成第二沟槽。在形成翅片之后，形成第三绝缘膜以填充第二沟槽并支撑翅片。然后去除第一绝缘膜的一部分以打开翅片之间的空间，其中可以形成包括栅极电介质，栅电极和附加接触，绝缘和存储节点结构的附加结构。

19. 发明授权

US08524590B2 Memory device and method for manufacturing memory devices 失效
标题翻译：用于制造存储器件的存储器件和方法
公开(公告)号：US08524590B2
公开(公告)日：2013-09-03
申请号：US13081849
申请日：2011-04-07
申请人： Suk-Joon Son , Eun-Suk Cho
发明人： Suk-Joon Son , Eun-Suk Cho
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L21/0206 , H01L21/02071 , H01L27/11521
摘要： Provided are a method for manufacturing a memory device and a memory device manufactured by the method. The memory device may be a flash memory device. The method for manufacturing the memory device may include sequentially stacking a tunnel dielectric, a floating gate conductive layer, an inter-gate dielectric, and a control gate conductive layer on a semiconductor substrate; anisotropically etching the floating gate conductive layer, the inter-gate dielectric, and the control gate conductive layer to form gate structures. The gate structures may be separated by regions where top surfaces of the tunnel dielectric are exposed, the exposed top surfaces being damaged during formation of the gate structures. The method includes reacting the exposed top surfaces of the tunnel dielectric damaged during the formation of the gate structures with a reaction gas comprising ammonium fluoride to form a reaction by-product on the exposed top surfaces of the tunnel dielectric, and removing the reaction by-product.
摘要翻译：提供一种用于制造通过该方法制造的存储器件和存储器件的方法。存储器件可以是闪存器件。用于制造存储器件的方法可以包括在半导体衬底上依次层叠隧道电介质，浮栅导电层，栅极间电介质和控制栅导电层; 各向异性蚀刻浮栅导电层，栅极间电介质和控制栅极导电层以形成栅极结构。栅极结构可以由隧道电介质的顶表面暴露的区域分开，暴露的顶表面在栅极结构的形成期间被损坏。该方法包括使形成栅极结构期间损坏的隧道电介质的暴露的顶表面与包含氟化铵的反应气体反应，以在隧道电介质的暴露的顶表面上形成反应副产物，产品。

20. 发明授权

US07807517B2 Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions 有权
标题翻译：制造具有对应于一对鳍型沟道区的单个栅电极的半导体器件的方法
公开(公告)号：US07807517B2
公开(公告)日：2010-10-05
申请号：US12219737
申请日：2008-07-28
申请人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
发明人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/785 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/10873 , H01L27/10879 , H01L27/1159 , H01L27/2436 , H01L29/66795
摘要： Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.
摘要翻译：提供了制造具有提供体偏置控制的鳍式FET结构的半导体器件的方法，显示出与SOI结构相关的一些特征优点，提供增加的工作电流和/或降低的接触电阻。制造半导体器件的方法包括在第一绝缘膜的突出部分的侧壁上形成绝缘间隔物; 通过使用绝缘间隔物作为蚀刻掩模去除半导体衬底的暴露区域，从而形成与第一绝缘膜接触并由第一绝缘膜支撑的鳍形成第二沟槽。在形成翅片之后，形成第三绝缘膜以填充第二沟槽并支撑翅片。然后去除第一绝缘膜的一部分以打开翅片之间的空间，其中可以形成包括栅极电介质，栅电极和附加接触，绝缘和存储节点结构的附加结构。

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