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11. 发明授权

US07208425B2 Method using TEOS ramp-up during TEOS/ozone CVD for improved gap-fill 有权
标题翻译：在TEOS /臭氧CVD期间使用TEOS上升的方法来改善间隙填充
公开(公告)号：US07208425B2
公开(公告)日：2007-04-24
申请号：US11367866
申请日：2006-03-03
申请人： Nitin K. Ingle , Xinyua Xia , Zheng Yuan
发明人： Nitin K. Ingle , Xinyua Xia , Zheng Yuan
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： C23C16/45523 , C23C16/045 , C23C16/401 , C23C16/402 , C23C16/45512 , C23C16/52 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/31612 , H01L21/76801 , Y10S438/958
摘要： Embodiments of the present invention provide methods, apparatuses, and devices related to chemical vapor deposition of silicon oxide. In one embodiment, a single-step deposition process is used to efficiently form a silicon oxide layer exhibiting high conformality and favorable gap-filling properties. During a pre-deposition gas flow stabilization phase and an initial deposition stage, a relatively low ratio of silicon-containing gas:oxidant deposition gas is flowed, resulting in formation of highly conformal silicon oxide at relatively slow rates. Over the course of the deposition process step, the ratio of silicon-containing gas:oxidant gas is increased, resulting in formation of less-conformal oxide material at relatively rapid rates during later stages of the deposition process step.
摘要翻译：本发明的实施例提供了与氧化硅的化学气相沉积相关的方法，装置和装置。在一个实施例中，使用单步沉积工艺来有效地形成表现出高共形性和良好间隙填充性能的氧化硅层。在预沉积气体流动稳定阶段和初始沉积阶段期间，含硅气体：氧化剂沉积气体的比例相对较低，从而以相对较慢的速率形成高度保形的氧化硅。在沉积工艺步骤的过程中，含硅气体：氧化剂气体的比率增加，导致在沉积工艺步骤的后续阶段以相对较快的速率形成较小保形的氧化物材料。

12. 发明授权

US07037859B2 Method using TEOS ramp-up during TEOS/ozone CVD for improved gap-fill 有权
标题翻译：在TEOS /臭氧CVD期间使用TEOS上升的方法来改善间隙填充
公开(公告)号：US07037859B2
公开(公告)日：2006-05-02
申请号：US10979471
申请日：2004-11-01
申请人： Nitin K. Ingle , Xinyua Xia , Zheng Yuan
发明人： Nitin K. Ingle , Xinyua Xia , Zheng Yuan
IPC分类号： H01L21/31
CPC分类号： C23C16/45523 , C23C16/045 , C23C16/401 , C23C16/402 , C23C16/45512 , C23C16/52 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/31612 , H01L21/76801 , Y10S438/958
摘要： Embodiments of the present invention provide methods, apparatuses, and devices related to chemical vapor deposition of silicon oxide. In one embodiment, a single-step deposition process is used to efficiently form a silicon oxide layer exhibiting high conformality and favorable gap-filling properties. During a pre-deposition gas flow stabilization phase and an initial deposition stage, a relatively low ratio of silicon-containing gas:oxidant deposition gas is flowed, resulting in formation of highly conformal silicon oxide at relatively slow rates. Over the course of the deposition process step, the ratio of silicon-containing gas:oxidant gas is increased, resulting in formation of less-conformal oxide material at relatively rapid rates during later stages of the deposition process step.
摘要翻译：本发明的实施例提供了与氧化硅的化学气相沉积相关的方法，装置和装置。在一个实施例中，使用单步沉积工艺来有效地形成表现出高共形性和良好间隙填充性能的氧化硅层。在预沉积气体流动稳定阶段和初始沉积阶段期间，含硅气体：氧化剂沉积气体的比例相对较低，从而以相对较慢的速率形成高度保形的氧化硅。在沉积工艺步骤的过程中，含硅气体：氧化剂气体的比率增加，导致在沉积工艺步骤的后续阶段以相对较快的速率形成较小保形的氧化物材料。

13. 发明申请

US20110151676A1 METHODS OF THIN FILM PROCESS 审中-公开
标题翻译：薄膜工艺方法
公开(公告)号：US20110151676A1
公开(公告)日：2011-06-23
申请号：US13039724
申请日：2011-03-03
申请人： Nitin K. Ingle , Jing Tang , Yi Zheng , Zheng Yuan , Zhenbin Ge , Xinliang Lu , Chien-Teh Kao , Vikash Banthia , William H. McClintock , Mei Chang
发明人： Nitin K. Ingle , Jing Tang , Yi Zheng , Zheng Yuan , Zhenbin Ge , Xinliang Lu , Chien-Teh Kao , Vikash Banthia , William H. McClintock , Mei Chang
IPC分类号： H01L21/31
CPC分类号： H01L21/67253 , H01L21/02164 , H01L21/0217 , H01L21/3105 , H01L21/31116 , H01L21/76232
摘要： A method for forming a semiconductor structure includes forming a plurality of features across a surface of a substrate, with at least one space being between two adjacent features. A first dielectric layer is formed on the features and within the at least one space. A portion of the first dielectric layer interacts with a reactant derived from a first precursor and a second precursor to form a first solid product. The first solid product is decomposed to substantially remove the portion of the first dielectric layer. A second dielectric layer is formed to substantially fill the at least one space.
摘要翻译：一种用于形成半导体结构的方法包括跨越衬底的表面形成多个特征，其中至少一个空间位于两个相邻特征之间。第一电介质层形成在特征上并且在至少一个空间内。第一介电层的一部分与衍生自第一前体和第二前体的反应物相互作用以形成第一固体产物。第一固体产物被分解以基本上除去第一介电层的部分。形成第二电介质层以基本上填充至少一个空间。

14. 发明授权

US07674684B2 Deposition methods for releasing stress buildup 有权
标题翻译：释放压力累积的沉积方法
公开(公告)号：US07674684B2
公开(公告)日：2010-03-09
申请号：US12178051
申请日：2008-07-23
申请人： Jing Tang , Nitin K. Ingle , Zheng Yuan , Rossella Mininni
发明人： Jing Tang , Nitin K. Ingle , Zheng Yuan , Rossella Mininni
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A deposition method for releasing a stress buildup of a feature over a semiconductor substrate with dielectric material is provided. The feature includes lines separated by a gap. The method includes forming a liner layer over the feature on the semiconductor substrate in a chamber. A stress of the liner layer over the feature is released to substantially reduce bending of the lines of the feature. A dielectric film is deposited over the stress-released liner layer to substantially fill the gap of the feature.
摘要翻译：提供了一种通过电介质材料释放在半导体衬底上的特征的应力累积的沉积方法。该功能包括由间隙隔开的线。该方法包括在腔室中的半导体衬底上的特征上形成衬垫层。衬垫层在特征上的应力被释放，以显着减少特征线的弯曲。电介质膜沉积在应力释放衬垫层上，以基本上填充特征的间隙。

15. 发明申请

US20100022067A1 DEPOSITION METHODS FOR RELEASING STRESS BUILDUP 有权
标题翻译：用于释放应力建筑的沉积方法
公开(公告)号：US20100022067A1
公开(公告)日：2010-01-28
申请号：US12178051
申请日：2008-07-23
申请人： Jing Tang , Nitin K. Ingle , Zheng Yuan , Rossella Mininni
发明人： Jing Tang , Nitin K. Ingle , Zheng Yuan , Rossella Mininni
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： A deposition method for releasing a stress buildup of a feature over a semiconductor substrate with dielectric material is provided. The feature includes lines separated by a gap. The method includes forming a liner layer over the feature on the semiconductor substrate in a chamber. A stress of the liner layer over the feature is released to substantially reduce bending of the lines of the feature. A dielectric film is deposited over the stress-released liner layer to substantially fill the gap of the feature.
摘要翻译：提供了一种通过电介质材料释放在半导体衬底上的特征的应力累积的沉积方法。该功能包括由间隙隔开的线。该方法包括在腔室中的半导体衬底上的特征上形成衬垫层。衬垫层在特征上的应力被释放，以显着减少特征线的弯曲。电介质膜沉积在应力释放衬垫层上，以基本上填充特征的间隙。

16. 发明授权

US07642171B2 Multi-step anneal of thin films for film densification and improved gap-fill 有权
标题翻译：用于膜致密化和改善间隙填充的薄膜的多步退火
公开(公告)号：US07642171B2
公开(公告)日：2010-01-05
申请号：US10990002
申请日：2004-11-16
申请人： Nitin K. Ingle , Zheng Yuan , Vikash Banthia , Xinyun Xia , Hali J. L. Forstner , Rong Pan
发明人： Nitin K. Ingle , Zheng Yuan , Vikash Banthia , Xinyun Xia , Hali J. L. Forstner , Rong Pan
IPC分类号： H01L21/76
CPC分类号： H01L21/324 , H01L21/02164 , H01L21/02271 , H01L21/02337 , H01L21/31612 , H01L21/31662 , H01L21/67115 , H01L21/76224 , H01L21/76283
摘要： A method of annealing a substrate comprising a trench containing a dielectric material, the method including annealing the substrate at a first temperature of about 200° C. to about 800° C. in a first atmosphere comprising an oxygen containing gas, and annealing the substrate at a second temperature of about 800° C. to about 1400° C. in a second atmosphere lacking oxygen. In addition, a method of annealing a substrate comprising a trench containing a dielectric material, the method including annealing the substrate at a first temperature of about 400° C. to about 800° C. in the presence of an oxygen containing gas, purging the oxygen containing gas away from the substrate, and raising the substrate to a second temperature from about 900° C. to about 1100° C. to further anneal the substrate in an atmosphere that lacks oxygen.
摘要翻译：一种退火包括含有电介质材料的沟槽的衬底的方法，所述方法包括在包含含氧气体的第一气氛中在大约200℃至大约800℃的第一温度下对衬底退火，以及退火衬底在约800℃至约1400℃的第二温度下在不含氧气的第二气氛中。另外，包括含有电介质材料的沟槽的衬底的退火方法，该方法包括在含氧气体存在下，在约400℃至约800℃的第一温度下退火衬底，含氧气体离开衬底，并将衬底升高至约900℃至约1100℃的第二温度，以在缺氧的气氛中进一步对衬底进行退火。

17. 发明申请

US20080182382A1 METHODS OF THIN FILM PROCESS 有权
标题翻译：薄膜工艺方法
公开(公告)号：US20080182382A1
公开(公告)日：2008-07-31
申请号：US11947674
申请日：2007-11-29
申请人： Nitin K. Ingle , Jing Tang , Yi Zheng , Zheng Yuan , Zhenbin Ge , Xinliang Lu , Chien-Teh Kao , Vikash Banthia , William H. McClintock , Mei Chang
发明人： Nitin K. Ingle , Jing Tang , Yi Zheng , Zheng Yuan , Zhenbin Ge , Xinliang Lu , Chien-Teh Kao , Vikash Banthia , William H. McClintock , Mei Chang
IPC分类号： H01L21/762
CPC分类号： H01L21/67253 , H01L21/02164 , H01L21/0217 , H01L21/3105 , H01L21/31116 , H01L21/76232
摘要： A method for forming a semiconductor structure includes forming a plurality of features across a surface of a substrate, with at least one space being between two adjacent features. A first dielectric layer is formed on the features and within the at least one space. A portion of the first dielectric layer interacts with a reactant derived from a first precursor and a second precursor to form a first solid product. The first solid product is decomposed to substantially remove the portion of the first dielectric layer. A second dielectric layer is formed to substantially fill the at least one space.
摘要翻译：一种用于形成半导体结构的方法包括跨越衬底的表面形成多个特征，其中至少一个空间位于两个相邻特征之间。第一电介质层形成在特征上并且在至少一个空间内。第一介电层的一部分与衍生自第一前体和第二前体的反应物相互作用以形成第一固体产物。第一固体产物被分解以基本上除去第一介电层的部分。形成第二电介质层以基本上填充至少一个空间。

18. 发明授权

US06905940B2 Method using TEOS ramp-up during TEOS/ozone CVD for improved gap-fill 有权
标题翻译：在TEOS /臭氧CVD期间使用TEOS上升的方法来改善间隙填充
公开(公告)号：US06905940B2
公开(公告)日：2005-06-14
申请号：US10247672
申请日：2002-09-19
申请人： Nitin K. Ingle , Xinyua Xia , Zheng Yuan
发明人： Nitin K. Ingle , Xinyua Xia , Zheng Yuan
IPC分类号： C23C16/40 , C23C16/44 , C23C16/455 , C23C16/52 , H01L21/762
CPC分类号： C23C16/45523 , C23C16/045 , C23C16/401 , C23C16/402 , C23C16/45512 , C23C16/52 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/31612 , H01L21/76801 , Y10S438/958
摘要： Embodiments of the present invention provide methods, apparatuses, and devices related to chemical vapor deposition of silicon oxide. In one embodiment, a single-step deposition process is used to efficiently form a silicon oxide layer exhibiting high conformality and favorable gap-filling properties. During a pre-deposition gas flow stabilization phase and an initial deposition stage, a relatively low ratio of silicon-containing gas:oxidant deposition gas is flowed, resulting in formation of highly conformal silicon oxide at relatively slow rates. Over the course of the deposition process step, the ratio of silicon-containing gas:oxidant gas is increased, resulting in formation of less-conformal oxide material at relatively rapid rates during later stages of the deposition process step.
摘要翻译：本发明的实施例提供了与氧化硅的化学气相沉积相关的方法，装置和装置。在一个实施例中，使用单步沉积工艺来有效地形成表现出高共形性和良好间隙填充性能的氧化硅层。在预沉积气体流动稳定阶段和初始沉积阶段期间，含硅气体：氧化剂沉积气体的比例相对较低，从而以相对较慢的速率形成高度保形的氧化硅。在沉积工艺步骤的过程中，含硅气体：氧化剂气体的比率增加，导致在沉积工艺步骤的后续阶段以相对较快的速率形成较小保形的氧化物材料。

19. 发明授权

US06544345B1 Method and system for in-situ cleaning of semiconductor manufacturing equipment using combination chemistries 失效
标题翻译：使用组合化学物质对半导体制造设备进行原位清洗的方法和系统
公开(公告)号：US06544345B1
公开(公告)日：2003-04-08
申请号：US09615035
申请日：2000-07-12
申请人： Bruce E. Mayer , Robert H. Chatham, III , Nitin K. Ingle , Zheng Yuan
发明人： Bruce E. Mayer , Robert H. Chatham, III , Nitin K. Ingle , Zheng Yuan
IPC分类号： B08B704
CPC分类号： B08B7/0035 , C23C16/4405 , Y10S438/905
摘要： An in-situ, two step or combination, method and system for cleaning of semiconductor manufacturing equipment is provided. The present invention utilizes two separate fluorine based chemistries in each step which selectively target the removal of different types of deposits that build up on the equipment surfaces. In particular, powdery and dense film-like solid deposits, as well as a combination of both, build up on the chamber surfaces and associated equipment components. These two types of deposits are removed selectively by the present invention. Such selective targeting of combined cleaning steps, yields an improved cleaning technique. In another embodiment, the method and system of the present invention provides for cleaning of the chamber and associated equipment using separate steps with different chemicals, and then performing these steps in a variety of desired sequences.
摘要翻译：提供了现场，两步或组合，半导体制造设备的清洁方法和系统。本发明在每个步骤中使用两个单独的基于氟的化学物质，其选择性地靶向在设备表面上积累的不同类型的沉积物的去除。特别地，粉末和致密的膜状固体沉积物以及两者的组合积聚在室表面和相关的设备部件上。这两种沉积物通过本发明有选择地被去除。组合清洁步骤的这种选择性靶向产生改进的清洁技术。在另一个实施方案中，本发明的方法和系统提供了使用具有不同化学物质的分离步骤清洁腔室和相关设备，然后以各种期望的顺序执行这些步骤。

20. 发明授权

US07087497B2 Low-thermal-budget gapfill process 有权
标题翻译：低热量预算的填隙过程
公开(公告)号：US07087497B2
公开(公告)日：2006-08-08
申请号：US10793559
申请日：2004-03-04
申请人： Zheng Yuan , Reza Arghavani , Ellie Y Yieh , Shankar Venkataraman
发明人： Zheng Yuan , Reza Arghavani , Ellie Y Yieh , Shankar Venkataraman
IPC分类号： H01L21/336
CPC分类号： H01L21/76224 , C23C16/403 , C23C16/45536 , C23C16/45544 , H01J37/32009 , H01L21/02178 , H01L21/0228 , H01L21/32055 , H01L21/67017 , H01L21/6719 , H01L21/763
摘要： A low-thermal-budget gapfill process is provided for filling a gap formed between two adjacent raised features on a strained-silicon substrate as part of a shallow-trench-isolation process. An electrically insulating liner is deposited using atomic-layer deposition and polysilicon is deposited over the electrically insulating liner, with both stages being conducted at temperatures below 700° C.
摘要翻译：提供了一种低热预算的间隙填充方法，用于填充在应变硅衬底上形成的两个相邻隆起特征之间的间隙，作为浅沟槽隔离工艺的一部分。使用原子层沉积沉积电绝缘衬垫，并且将多晶硅沉积在电绝缘衬垫上，其中两个阶段在低于700℃的温度下进行。

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