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11. 发明申请

US20160086299A1 Position-Only Shading Pipeline 有权
标题翻译：仅定位着色管道
公开(公告)号：US20160086299A1
公开(公告)日：2016-03-24
申请号：US14494653
申请日：2014-09-24
申请人： Saurabh Sharma , Subramaniam Maiyuran , Thomas A. Piazza , Kalyan K. Bhiravabhatla , Peter L. Doyle , Paul A. Johnson , Bimal Poddar , Jon N. Hasselgren , Carl J. Munkberg , Tomas G. Akenine-Moller , Harri Syrja , Kevin Rogovin , Robert L. Farrell
发明人： Saurabh Sharma , Subramaniam Maiyuran , Thomas A. Piazza , Kalyan K. Bhiravabhatla , Peter L. Doyle , Paul A. Johnson , Bimal Poddar , Jon N. Hasselgren , Carl J. Munkberg , Tomas G. Akenine-Moller , Harri Syrja , Kevin Rogovin , Robert L. Farrell
IPC分类号： G06T1/20 , G06T15/40
CPC分类号： G06T1/20 , G06T15/40 , G06T15/405 , G06T15/503 , G09G5/393
摘要： In position-only shading, two geometry pipes exist, a trimmed down version called the Cull Pipe and a full version called the Replay Pipe. Thus, the Cull Pipe executes the position shaders in parallel with the main application, but typically generates the critical results much faster as it fetches and shades only the position attribute of the vertices and avoids the rasterization as well as the rendering of pixels for the frame buffer. Furthermore, the Cull Pipe uses these critical results to compute visibility information for all the triangles whether they are culled or not. On the other hand, the Replay Pipe consumes the visibility information to skip the culled triangles and shades only the visible triangles that are finally passed to the rasterization phase. Together the two pipes can hide the long cull runs of discarded triangles and can complete the work faster in some embodiments.
摘要翻译：在仅位置阴影中，存在两个几何管道，一个称为Cull管道的修剪版本以及称为Replay Pipe的完整版本。因此，Cull管道与主应用程序并行执行位置着色器，但是通常会生成关键结果的速度要快得多，因为它仅获取和仅阴影顶点的位置属性，并避免光栅化以及帧的像素渲染缓冲。此外，Cull管道使用这些关键结果来计算所有三角形的可见性信息，无论它们是否被淘汰。另一方面，重放管道消耗可见性信息来跳过被剔除的三角形，并仅遮蔽最终传递到光栅化阶段的可见三角形。两个管道一起可以隐藏丢弃的三角形的长的剔除运行，并且在一些实施例中可以更快地完成工作。

12. 发明授权

US08544019B2 Thread queueing method and apparatus 有权
标题翻译：线程排队方法和设备
公开(公告)号：US08544019B2
公开(公告)日：2013-09-24
申请号：US13116245
申请日：2011-05-26
申请人： Hong Jiang , Thomas A. Piazza , Brian D. Rauchfuss , Sreedevi Chalasani , Steven J. Spangler
发明人： Hong Jiang , Thomas A. Piazza , Brian D. Rauchfuss , Sreedevi Chalasani , Steven J. Spangler
IPC分类号： G06F9/46 , G06F15/00
CPC分类号： G06F9/546
摘要： In some embodiments, a method includes receiving a request to generate a thread and supplying a request to a queue in response at least to the received request. The method may further include fetching a plurality of instructions in response at least in part to the request supplied to the queue and executing at least one of the plurality of instructions. In some embodiments, an apparatus includes a storage medium having stored therein instructions that when executed by a machine result in the method. In some embodiments, an apparatus includes circuitry to receive a request to generate a thread and to queue a request to generate a thread in response at least to the received request. In some embodiments, a system includes circuitry to receive a request to generate a thread and to queue a request to generate a thread in response at least to the received request, and a memory unit to store at least one instruction for the thread.
摘要翻译：在一些实施例中，一种方法包括接收生成线程的请求并至少响应于所接收的请求向队列提供请求。该方法还可以包括至少部分地响应于提供给队列的请求并且执行多个指令中的至少一个指令来获取多个指令。在一些实施例中，装置包括存储介质，其中存储有当机器执行时产生该方法的指令。在一些实施例中，一种装置包括用于接收生成线程的请求并至少对接收到的请求作出响应来排队请求生成线程的电路。在一些实施例中，系统包括电路，用于接收生成线程的请求，并至少响应于所接收到的请求来对请求进行排队以生成线程;以及存储器单元，用于存储线程的至少一条指令。

13. 发明申请

US20120272032A1 Dynamic Allocation of a Buffer Across Multiple Clients in a Threaded Processor 有权
标题翻译：螺纹处理器中多个客户端的缓冲区的动态分配
公开(公告)号：US20120272032A1
公开(公告)日：2012-10-25
申请号：US13534259
申请日：2012-06-27
申请人： Thomas A. Piazza
发明人： Thomas A. Piazza
IPC分类号： G06F12/02
CPC分类号： G06F9/5016 , G06F12/023
摘要： A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using the ranges of addresses. Different ranges of addresses in the memory may be redistributed among a second set of functions in a second pipeline without waiting for the first set of functions to be flushed of data.
摘要翻译：一种方法可以包括在第一流水线中的第一组函数中分配存储器中的地址范围。第一管道中的第一组功能可以使用地址范围对数据进行操作。可以在第二流水线中的第二组功能中重新分配存储器中的不同范围的地址，而不等待第一组功能被刷新数据。

14. 发明授权

US07035984B2 Memory arbiter with grace and ceiling periods and intelligent page gathering logic 失效
公开(公告)号：US07035984B2
公开(公告)日：2006-04-25
申请号：US10038941
申请日：2001-12-31
申请人： Josh B. Mastronarde , Aditya Sreenivas , Thomas A. Piazza
发明人： Josh B. Mastronarde , Aditya Sreenivas , Thomas A. Piazza
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F13/1642
摘要： Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.

15. 发明授权

US06760031B1 Upgrading an integrated graphics subsystem 有权
标题翻译：升级集成图形子系统
公开(公告)号：US06760031B1
公开(公告)日：2004-07-06
申请号：US09476658
申请日：1999-12-31
申请人： Brian K. Langendorf , Thomas A. Piazza
发明人： Brian K. Langendorf , Thomas A. Piazza
IPC分类号： G06F1516
CPC分类号： G06F3/14 , G06F3/1438 , G09G5/363 , G09G5/393 , G09G2352/00 , G09G2360/06
摘要： Apparatus and methods are provided for allowing two graphics controllers to cooperate on a single screen and for modifying the AGP protocol to provide symmetric capabilities for both AGP targets and AGP masters. According to one embodiment of the present invention two graphics controllers may cooperate as one virtual graphics controller. A first graphics controller renders a first subset of pixels of a display to a local memory of the first graphics controller. A second graphics controller renders a second subset of pixels of the display to a local memory of the second graphics controller. Then, after both the first graphics controller and the second graphics controller have completed their respective rendering, merging the content of the local memory of the first graphics controller and the content of the local memory of the second graphics controller.
摘要翻译：提供了装置和方法，用于允许两个图形控制器在单个屏幕上协作并且用于修改AGP协议以为AGP目标和AGP主机提供对称能力。根据本发明的一个实施例，两个图形控制器可以协作为一个虚拟图形控制器。第一图形控制器将显示器的像素的第一子集渲染到第一图形控制器的本地存储器。第二图形控制器将显示器的像素的第二子集呈现给第二图形控制器的本地存储器。然后，在第一图形控制器和第二图形控制器都已经完成它们各自的渲染之后，合并第一图形控制器的本地存储器的内容和第二图形控制器的本地存储器的内容。

16. 发明授权

US06330646B1 Arbitration mechanism for a computer system having a unified memory architecture 有权
标题翻译：具有统一存储架构的计算机系统的仲裁机制
公开(公告)号：US06330646B1
公开(公告)日：2001-12-11
申请号：US09226965
申请日：1999-01-08
申请人： Steve J. Clohset , Trung A. Diep , Wishwesh A. Gandhi , Thomas A. Piazza , Aditya Sreenivas , Tuong P. Trieu
发明人： Steve J. Clohset , Trung A. Diep , Wishwesh A. Gandhi , Thomas A. Piazza , Aditya Sreenivas , Tuong P. Trieu
IPC分类号： G06F1300
CPC分类号： G06F13/18
摘要： According to one embodiment, a computer system is disclosed that includes a memory and a memory controller coupled to the memory. The memory controller includes an arbitration unit that may be programmed to operate according to a first arbitration mode or a second arbitration mode. The computer system also includes a first device and a second device coupled to the arbitration unit. According to a further embodiment, the first device is assigned a higher priority classification than the second device for accessing the memory while the arbitration unit is operating according to the first arbitration mode. In addition, the first device and the second device are assigned equal priority classifications for accessing the memory while the arbitration unit is operating according to the second arbitration mode.
摘要翻译：根据一个实施例，公开了一种包括存储器和耦合到存储器的存储器控制器的计算机系统。存储器控制器包括可被编程为根据第一仲裁模式或第二仲裁模式进行操作的仲裁单元。计算机系统还包括耦合到仲裁单元的第一设备和第二设备。根据另一实施例，当仲裁单元根据第一仲裁模式操作时，第一设备被分配比用于访问存储器的第二设备更高的优先级分类。此外，当仲裁单元根据第二仲裁模式操作时，第一设备和第二设备被分配用于访问存储器的相同的优先级分类。

17. 发明授权

US06204857B1 Method and apparatus for effective level of detail selection 失效
标题翻译：有效的细节选择水平的方法和装置
公开(公告)号：US06204857B1
公开(公告)日：2001-03-20
申请号：US09061383
申请日：1998-04-16
申请人： Thomas A. Piazza , Michael Mantor , Ralph Clayton Taylor , Val Gene Cook
发明人： Thomas A. Piazza , Michael Mantor , Ralph Clayton Taylor , Val Gene Cook
IPC分类号： G06T1140
CPC分类号： G06T15/04
摘要： Method and apparatus for rendering texture to an object to be displayed on a pixel screen display. This technique makes use of linear interpolation between perspectively correct texture address to calculate rates of change of individual texture addresses components to determine a selection of the correct LOD map to use and intermediate texture addresses for pixels of the object between the perspectively correct addresses. The method first determines perspectively correct texture address values associated with four corners of a predefined span or grid of pixels. Then, a linear interpolation technique is implemented to calculate a rate of change of texture address components in the screen x and y directions for pixels between the perspectively bound span corners. This linear interpolation technique is performed in both screen directions to thereby create a potentially unique level of detail value for each pixel, which is then used as an index to select the correct pre-filtered LOD texture map. When mapping an individually determined LOD value per pixel, the effect of producing undesirable artifacts that may appear if a single LOD for an entire span or polygon is used, is obviated.
摘要翻译：用于将纹理渲染到要在像素屏幕显示上显示的对象的方法和装置。该技术利用透视正确的纹理地址之间的线性插值来计算各个纹理地址分量的变化率，以确定正确的LOD映射的使用选择，以及在透视正确的地址之间对象的像素的中间纹理地址。该方法首先确定与预定义跨度或像素网格的四个角相关联的透视正确的纹理地址值。然后，实现线性插值技术，以计算在透视边界角之间的像素的屏幕x和y方向上的纹理地址分量的变化率。这种线性插值技术在两个屏幕方向上执行，从而为每个像素创建潜在唯一的细节值级，然后将其用作选择正确的预滤波LOD纹理图的索引。当映射每个像素的单独确定的LOD值时，如果使用整个跨度或多边形的单个LOD，则可能出现产生不期望的伪影的效果。

18. 发明授权

US5367615A Spatial augmentation of vertices and continuous level of detail transition for smoothly varying terrain polygon density 失效
标题翻译：对于平滑变化的地形多边形密度，顶点的空间增加和细节过渡的连续水平
公开(公告)号：US5367615A
公开(公告)日：1994-11-22
申请号：US115727
申请日：1993-09-02
申请人： Richard Economy , William A. Kelly , Anthony J. Pelham , Thomas A. Piazza , Lee T. Quick
发明人： Richard Economy , William A. Kelly , Anthony J. Pelham , Thomas A. Piazza , Lee T. Quick
IPC分类号： G06T15/50 , G06F15/62
CPC分类号： G06T15/50
摘要： In a computer image generation system, the number of vertices which define each of a plurality of terrain-defining polygons is augmented in real time for providing finer detail and for effecting substantially continuous smooth level of detail (LOD) transition. Augmented vertices may have components that are statistically derived, in which case it is not necessary to store and/or predefine them. Alternatively, some vertex components may have predetermined values derived from mapping data or from other deterministic sources and may be stored in compact form. Processing polygons, typically triangles defined by selected ones of the sum of the augmented vertices and the original vertices, may be used for displaying the finer detail. Statistically derived finer detail is especially suited for providing non-specific detail to features such as terrain, while deterministic data allows highly accurate representations of specific `real world` locations. The decision to augment vertices is controlled by a predetermined breakup criteria, which may be selected as one, or a combination, of: range from the viewpoint; angle from the viewpoint boresight; desired maximum error; and other defined criteria.
摘要翻译：在计算机图像生成系统中，实时地增加了限定多个地形限定多边形中的每一个的顶点的数量，以提供更细的细节并且实现基本上连续的平滑的细节级别（LOD）转换。增强顶点可能具有统计学导出的组件，在这种情况下，不需要存储和/或预定义它们。或者，一些顶点分量可以具有从映射数据或来自其他确定性源导出的预定值，并且可以以紧凑形式存储。处理多边形，通常由增加的顶点和原始顶点之和中的选定的三角形定义的三角形，可用于显示更细的细节。统计得出更精细的细节特别适用于为诸如地形等特征提供非特定细节，而确定性数据允许特定“真实世界”位置的高度准确表示。增加顶点的决定由预定的分解标准控制，预定的分解标准可以被选择为以下一个或组合：从视点的范围; 从视点视线角度; 期望最大误差; 和其他定义的标准。

19. 发明授权

US10297001B2 Reduced power implementation of computer instructions 有权
公开(公告)号：US10297001B2
公开(公告)日：2019-05-21
申请号：US14583300
申请日：2014-12-26
申请人： Subramaniam Maiyuran , Shubh B. Shah , Ashutosh Garg , Jin Xu , Thomas A. Piazza , Jorge F. Garcia Pabon , Michael K. Dwyer
发明人： Subramaniam Maiyuran , Shubh B. Shah , Ashutosh Garg , Jin Xu , Thomas A. Piazza , Jorge F. Garcia Pabon , Michael K. Dwyer
IPC分类号： G06T1/20 , G09G5/00 , G06T15/80 , G09G5/36 , G06F7/00 , G06F9/30
摘要： Systems and methods may provide a graphics processor that may identify operating conditions under which certain floating point instructions may utilize power to fewer hardware resources compared to when the instructions are executing under other operating conditions. The operating conditions may be determined by examining operands used in a given instruction, including the relative magnitudes of the operands and whether the operands may be taken as equal to certain defined values. The floating point instructions may include instructions for an addition operation, a multiplication operation, a compare operation, and/or a fused multiply-add operation.

20. 发明授权

US09245324B2 Lossy color merge for multi-sampling anti-aliasing compression 有权
标题翻译：有损色彩合并用于多采样抗锯齿压缩
公开(公告)号：US09245324B2
公开(公告)日：2016-01-26
申请号：US13901117
申请日：2013-05-23
申请人： Tomas G. Akenine-Moller , Thomas A. Piazza , Prasoonkumar Surti
发明人： Tomas G. Akenine-Moller , Thomas A. Piazza , Prasoonkumar Surti
IPC分类号： G06T5/00 , G06T11/40
CPC分类号： G06T5/002 , G06T9/00 , G06T11/40 , G06T15/503
摘要： Techniques related to graphics rendering including lossy color merge for multi-sampling anti-aliasing compression.
摘要翻译：与图形渲染相关的技术，包括用于多采样抗锯齿压缩的有损色彩合并。

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