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11. 发明申请

US20130008607A1 ANTENNA, DIELECTRIC WINDOW, PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD 有权
标题翻译：天线，电介质窗，等离子体加工设备和等离子体处理方法
公开(公告)号：US20130008607A1
公开(公告)日：2013-01-10
申请号：US13541940
申请日：2012-07-05
申请人： Naoki MATSUMOTO , Wataru YOSHIKAWA , Jun YOSHIKAWA , Kazuki MOYAMA , Kiyotaka ISHIBASHI , Osamu MORITA , Takehiro TANIKAWA
发明人： Naoki MATSUMOTO , Wataru YOSHIKAWA , Jun YOSHIKAWA , Kazuki MOYAMA , Kiyotaka ISHIBASHI , Osamu MORITA , Takehiro TANIKAWA
IPC分类号： H01Q13/10 , B05C11/00
CPC分类号： H01J37/32238
摘要： An antenna, a dielectric window, a plasma processing apparatus and a plasma processing method are capable of improving uniformity of a substrate surface processing amount in the surface of the substrate. The antenna includes the dielectric window 16; and a slot plate 20, provided on one side of the dielectric window 16, having a plurality of slots 133. The dielectric window 16 has a flat surface 146 surrounded by a ring-shaped first recess; and a plurality of second recesses 153 formed on the flat surface 146 so as to surround a center of the flat surface 146. Here, the flat surface 146 is formed on the other side of the dielectric window 16. When viewed from a thickness direction of the slot plate, a center of each second recess 153 is located within each slot 133 of the slot plate.
摘要翻译：天线，电介质窗，等离子体处理装置和等离子体处理方法能够提高基板表面的基板表面处理量的均匀性。天线包括电介质窗16; 以及设置在电介质窗口16的一侧上的槽板20，具有多个狭槽133.介电窗口16具有由环形的第一凹部包围的平坦表面146; 以及形成在平坦表面146上以围绕平坦表面146的中心的多个第二凹部153.这里，平坦表面146形成在电介质窗口16的另一侧。当从厚度方向槽板，每个第二凹槽153的中心位于槽板的每个槽133内。

12. 发明申请

US20130002070A1 MOTOR 有权
标题翻译：发动机
公开(公告)号：US20130002070A1
公开(公告)日：2013-01-03
申请号：US13533400
申请日：2012-06-26
申请人： Naoki MATSUMOTO
发明人： Naoki MATSUMOTO
IPC分类号： H02K11/02
CPC分类号： H02K11/026 , H02K5/225
摘要： A motor includes an armature, a yoke, and an end bracket. The yoke has a bottom and an open end and accommodates the armature. The end bracket substantially closes the open end of the yoke. A connector portion, which bulges outward of the yoke, and a cutout portion are formed in the circumferential wall of the end bracket. A pair of feed members is provided to extend from the interior of the end bracket to the connector portion through the cutout portion. Each feed member has a plurality of connection portions. Each of a pair of terminals of each of a plurality of noise suppression elements is connected to each connection portion. The connection portions are formed in the feed member and arranged in the radial direction.
摘要翻译：电动机包括电枢，轭和端支架。轭具有底部和开口端并容纳电枢。端托架基本上封闭轭架的开口端。在端托架的周壁上形成有一个连接部，该连接部从轭的外侧凸出，切口部形成。一对进给构件设置成通过切口部分从端托架的内部延伸到连接器部分。每个进料构件具有多个连接部分。多个噪声抑制元件中的每一个的一对端子中的每一个连接到每个连接部分。连接部分形成在馈送部件中并沿径向布置。

13. 发明申请

US20080296585A1 GROWTH METHOD OF GaN CRYSTAL, AND GaN CRYSTAL SUBSTRATE 失效
标题翻译： GaN晶体和GaN晶体衬底的生长方法
公开(公告)号：US20080296585A1
公开(公告)日：2008-12-04
申请号：US12130082
申请日：2008-05-30
申请人： Naoki MATSUMOTO , Fumitaka Sato , Seiji Nakahata , Takuji Okahisa , Koji Uematsu
发明人： Naoki MATSUMOTO , Fumitaka Sato , Seiji Nakahata , Takuji Okahisa , Koji Uematsu
IPC分类号： H01L29/207 , H01L21/205
CPC分类号： C30B29/406 , C30B25/20
摘要： A method of producing a GaN crystal is directed to growing a GaN crystal on a GaN seed crystal substrate. The method includes the steps of preparing a GaN seed crystal substrate including a first dopant such that the thermal expansion coefficient of the GaN seed crystal substrate becomes greater than that of the GaN crystal, and growing the GaN crystal to a thickness of at least 1 mm on the GaN seed crystal substrate. Accordingly, there can be provided a method of producing a GaN crystal that can suppress generation of a crack and grow a thick GaN crystal, and a GaN crystal substrate.
摘要翻译：制造GaN晶体的方法涉及在GaN晶种衬底上生长GaN晶体。该方法包括以下步骤：制备包括第一掺杂剂的GaN籽晶衬底，使得GaN晶种衬底的热膨胀系数变得大于GaN晶体的热膨胀系数，并将GaN晶体生长至至少1mm的厚度在GaN晶种衬底上。因此，可以提供一种能够抑制裂纹的产生和生长厚GaN的晶体的GaN晶体的制造方法以及GaN晶体基板。

14. 发明申请

US20130106450A1 DRIVE CIRCUIT AND TEST APPARATUS 审中-公开
标题翻译：驱动电路和测试装置
公开(公告)号：US20130106450A1
公开(公告)日：2013-05-02
申请号：US13562314
申请日：2012-07-31
申请人： Masashi WATANABE , Kensuke SOEDA , Naoki MATSUMOTO
发明人： Masashi WATANABE , Kensuke SOEDA , Naoki MATSUMOTO
IPC分类号： G05F5/00 , G01R31/28
CPC分类号： G01R31/31924
摘要： The response characteristics of an output signal and current consumption are kept constant. A drive circuit for outputting an output signal having a voltage determined by a logic of an input signal includes a constant voltage generating section generating a constant bias voltage, a CML circuit outputting the output signal having the voltage determined by the logic of the input signal, where an amplitude of the output signal is determined by a constant current flowing through the CML circuit and a potential of the output signal is determined by the bias voltage, an adjustment constant current source that allows a constant current to flow out from a bias voltage output end of the constant voltage generating section, and a current setting section that sets in advance the constant current flowing into the adjustment constant current source, according to the constant current flowing through the CML circuit.
摘要翻译：输出信号和电流消耗的响应特性保持不变。用于输出具有由输入信号的逻辑确定的电压的输出信号的驱动电路包括产生恒定偏置电压的恒压产生部分，输出具有由输入信号的逻辑确定的电压的输出信号的CML电路，其中输出信号的幅度由流过CML电路的恒定电流确定，并且输出信号的电位由偏置电压确定，允许恒定电流从偏置电压输出流出的调节恒流源恒定电压产生部分的端部和根据流过CML电路的恒定电流预先设定流入调节恒流源的恒定电流的电流设定部分。

15. 发明申请

US20130008609A1 PLASMA PROCESSING APPARATUS 审中-公开
标题翻译：等离子体加工设备
公开(公告)号：US20130008609A1
公开(公告)日：2013-01-10
申请号：US13618587
申请日：2012-09-14
申请人： Chishio KOSHIMIZU , Naoki MATSUMOTO , Satoshi TANAKA , Toru ITO
发明人： Chishio KOSHIMIZU , Naoki MATSUMOTO , Satoshi TANAKA , Toru ITO
IPC分类号： C23F1/08
CPC分类号： H01J37/21 , H01J37/32091 , H01J37/32155 , H01J37/32165 , H01J37/32348 , H01J37/32449 , H01J37/32467 , H01J37/32642 , H01J2237/21 , H01J2237/334
摘要： A plasma processing apparatus includes a processing chamber, a first electrode and a second electrode disposed to face each other, a high frequency power supply unit for applying a high frequency power to either the first electrode or the second electrode, a processing gas supply unit for supplying a processing gas to a processing space, and a main dielectric member provided at a substrate mounting portion on a main surface of the first electrode. A focus ring is attached to the first electrode to cover a peripheral portion of the main surface of the first electrode and a peripheral dielectric member is provided in a peripheral portion on the main surface of the first electrode so that an electrostatic capacitance per unit area applied between the first electrode and the focus ring is smaller than that applied between the first electrode and the substrate by the main dielectric member.
摘要翻译：等离子体处理装置包括处理室，第一电极和彼此相对配置的第二电极，用于向第一电极或第二电极施加高频电力的高频电源单元，用于将处理气体供给到处理空间，以及设置在第一电极的主表面上的基板安装部的主电介质部件。聚焦环安装在第一电极上以覆盖第一电极的主表面的周边部分，并且在第一电极的主表面的周边部分设置外围电介质构件，使得每单位面积的静电电容在第一电极和聚焦环之间的距离小于通过主电介质构件施加在第一电极和衬底之间的位置。

16. 发明申请

US20120319129A1 SUBSTRATE, EPITAXIAL LAYER PROVIDED SUBSTRATE, METHOD FOR PRODUCING SUBSTRATE, AND METHOD FOR PRODUCING EPITAXIAL LAYER PROVIDED SUBSTRATE 有权
标题翻译：基板，外延层提供的基板，生产基板的方法和用于生产外延层的基板的方法
公开(公告)号：US20120319129A1
公开(公告)日：2012-12-20
申请号：US13595583
申请日：2012-08-27
申请人： Naoki MATSUMOTO
发明人： Naoki MATSUMOTO
IPC分类号： H01L29/20
CPC分类号： C30B29/406 , C30B25/20 , H01L21/02395 , H01L21/0243 , H01L21/02458 , H01L21/0254 , H01L21/02642 , H01L21/02647 , H01L21/02658
摘要： The present invention provides a substrate formed at a low cost and having a controlled plate shape, an epitaxial layer provided substrate obtained by forming an epitaxial layer on the substrate, and methods for producing them. The method for producing the substrate according to the present invention includes an ingot growing step (S110) serving as a step of preparing an ingot formed of gallium nitride (GaN); and a slicing step (S120) serving as a step of obtaining a substrate formed of gallium nitride, by slicing the ingot. In the slicing step (S120), the substrate thus obtained by the slicing has a main surface with an arithmetic mean roughness Ra of not less than 0.05 μm and not more than 1 μm on a line of 10 mm.
摘要翻译：本发明提供一种以低成本形成并具有受控板形状的基板，通过在基板上形成外延层而获得的外延层提供的基板及其制造方法。本发明的基板的制造方法包括：制造由氮化镓（GaN）形成的铸锭的工序的铸锭生长工序（S110）。以及切片步骤（S120），其作为通过切割锭来获得由氮化镓形成的衬底的步骤。在切片工序（S120）中，通过切片得到的基板在10mm的线上具有算术平均粗糙度Ra为0.05μm以上且1μm以下的主面。

17. 发明申请

US20110121311A1 METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于制造半导体衬底的方法，制造半导体器件的方法，半导体衬底和半导体器件
公开(公告)号：US20110121311A1
公开(公告)日：2011-05-26
申请号：US12943545
申请日：2010-11-10
申请人： Fumitaka SATO , Akihiro HACHIGO , Naoki MATSUMOTO , Yoko MAEDA , Seiji NAKAHATA
发明人： Fumitaka SATO , Akihiro HACHIGO , Naoki MATSUMOTO , Yoko MAEDA , Seiji NAKAHATA
IPC分类号： H01L29/12 , H01L21/18
CPC分类号： H01L21/2654 , H01L21/76254 , H01L29/045 , H01L29/2003 , H01L29/66143 , H01L29/872
摘要： The present invention provides a method for manufacturing a semiconductor substrate including a low-resistance nitride layer laminated on a substrate, a method for manufacturing a semiconductor device, a semiconductor substrate, and a semiconductor device. A method for manufacturing a semiconductor substrate of the present invention includes the following steps: A nitride substrate having a principal surface and a back surface opposite to the principal surface is prepared. Vapor-phase ions are implanted into the back surface of the nitride substrate. The back surface of the nitride substrate is bonded to a dissimilar substrate to form a bonded substrate. The nitride substrate is partially separated from the bonded substrate to form a laminated substrate including the dissimilar substrate and a nitride layer. The laminated substrate is heat-treated at a temperature over 700° C.
摘要翻译：本发明提供了一种制造半导体衬底的方法，该半导体衬底包括层叠在衬底上的低电阻氮化物层，半导体器件的制造方法，半导体衬底和半导体器件。本发明的半导体衬底的制造方法包括以下步骤：准备具有与主面相反的主面和背面的氮化物衬底。气相离子注入到氮化物衬底的背表面中。氮化物衬底的背面与不同的衬底接合以形成键合衬底。氮化物衬底与键合衬底部分地分离以形成包括不同衬底和氮化物层的叠层衬底。层压基板在700℃以上的温度下进行热处理

18. 发明申请

US20100279440A1 NITRIDE SEMICONDUCTOR WAFER AND METHOD OF PROCESSING NITRIDE SEMICONDUCTOR WAFER 失效
标题翻译：氮化物半导体滤波器和氮化物半导体滤波器的处理方法
公开(公告)号：US20100279440A1
公开(公告)日：2010-11-04
申请号：US12836001
申请日：2010-07-14
申请人： Masahiro NAKAYAMA , Naoki MATSUMOTO , Koshi TAMAMURA , Masao IKEDA
发明人： Masahiro NAKAYAMA , Naoki MATSUMOTO , Koshi TAMAMURA , Masao IKEDA
IPC分类号： H01L21/66
CPC分类号： H01L21/02008 , B24B37/08 , H01L21/02024 , Y10S438/959
摘要： Nitride semiconductor wafers which are produced by epitaxially grown nitride films on a foreign undersubstrate in vapor phase have strong inner stress due to misfit between the nitride and the undersubstrate material. A GaN wafer which has made by piling GaN films upon a GaAs undersubstrate in vapor phase and eliminating the GaAs undersubstrate bends upward due to the inner stress owing to the misfit of lattice constants between GaN and GaAs. Ordinary one-surface polishing having the steps of gluing a wafer with a surface on a flat disc, bringing another surface in contact with a lower turntable, pressing the disc, rotating the disc, revolving the turntable and whetting the lower surface, cannot remedy the inherent distortion. The Distortion worsens morphology of epitaxial wafers, lowers yield of via-mask exposure and invites cracks on surfaces. Nitride crystals are rigid but fragile. Chemical/mechanical polishing has been requested in vain. Current GaN wafers have roughened bottom surfaces, which induce contamination of particles and fluctuation of thickness.Circular nitride wafers having a diameter larger than 45 mm are made and polished. Gross-polishing polishes the nitride wafers in a pressureless state with pressure less than 60 g/cm2 by lifting up the upper turntable for remedying distortion. Distortion height H at a center is reduced to H≦12 μm. Minute-polishing is a newly-contrived CMP which polishes the nitride wafers with a liquid including potassium hydroxide, potassium peroxodisulfate and powder, irradiates the potassium peroxodisulfate with ultraviolet rays. The CMP-polished top surface has roughness RMS of 0.1 nm≦RMS≦5 nm or more favorably 0.1 nm≦RMS≦0.5 nm. The CMP-polished bottom surface has roughness RMS of 0.1 nm≦RMS≦5000 nm or more favorably 0.1 nm≦RMS≦2 nm. TTV is less than 10 μm.
摘要翻译：由氮化物和下衬底材料之间的失配导致的，由外延生长的氮化物膜在气相中的外来下衬衬底产生的氮化物半导体晶片具有很强的内部应力。通过在气相中在GaAs下衬底上堆叠GaN膜而消除GaAs下衬层而制成的GaN晶片由于内部应力而由于GaN和GaAs之间的晶格常数的失配而向上弯曲。通常的单面抛光具有将晶片与平面盘上的表面胶合的步骤，使另一表面与下转台接触，按压盘，旋转盘，旋转转台并磨削下表面，不能补救固有失真。失真会加剧外延晶片的形态，降低通孔掩模曝光的产量，并引起表面裂纹。氮化物晶体是刚性但脆弱的。化学/机械抛光已被要求徒劳。当前的GaN晶圆已经粗糙化了底面，这引起了颗粒的污染和厚度的波动。制造和抛光直径大于45mm的圆形氮化物晶片。粗抛光通过提升上转盘来补偿变形，在压力小于60g / cm2的无压状态下抛光氮化物晶片。中心处的失真高度H降低到H＆nlE; 12μm。分钟抛光是一种新设计的CMP，它们用包括氢氧化钾，过氧硫酸钾和粉末的液体对氮化物晶片进行抛光，用紫外线照射过氧二硫酸钾。 CMP抛光的顶表面的粗糙度RMS为0.1nm＆nlE; RMS＆nlE; 5nm或更优选为0.1nm＆nlE; RMS＆nlE; 0.5nm。 CMP抛光的底表面的粗糙度RMS为0.1nm＆nlE; RMS＆nlE; 5000nm或更优选为0.1nm＆nlE; RMS＆nlE; 2nm。 TTV小于10微米。

19. 发明申请

US20130284371A1 CAPACITIVE COUPLING PLASMA PROCESSING APPARATUS AND METHOD FOR USING THE SAME 审中-公开
标题翻译：电容耦合等离子体处理装置及其使用方法
公开(公告)号：US20130284371A1
公开(公告)日：2013-10-31
申请号：US13932567
申请日：2013-07-01
申请人： Naoki MATSUMOTO , Chishio Koshimizu , Akira Koshiishi
发明人： Naoki MATSUMOTO , Chishio Koshimizu , Akira Koshiishi
IPC分类号： H01L21/67
CPC分类号： H01L21/67069 , C23F4/00 , H01J37/32082 , H01J37/3244 , H01J37/32532 , H01J2237/334
摘要： A plasma processing apparatus includes a process container configured to accommodate a target substrate and to be vacuum-exhausted. A first electrode and a second electrode are disposed opposite each other within the process container. The first electrode includes an outer portion and an inner portion both facing the second electrode such that the outer portion surrounds the inner portion. An RF power supply is configured to apply an RF power to the outer portion of the first electrode. A DC power supply is configured to apply a DC voltage to the inner portion of the first electrode. A process gas supply unit is configured to supply a process gas into the process container, wherein plasma of the process gas is generated between the first electrode and the second electrode.
摘要翻译：等离子体处理装置包括被配置为容纳目标基板并被抽真空的处理容器。第一电极和第二电极在处理容器内彼此相对设置。第一电极包括外部部分和面向第二电极的内部部分，使得外部部分围绕内部部分。 RF电源被配置为向第一电极的外部施加RF功率。 DC电源被配置为向第一电极的内部施加DC电压。处理气体供应单元被配置为将处理气体供应到处理容器中，其中处理气体的等离子体在第一电极和第二电极之间产生。

20. 发明申请

US20130008608A1 PLASMA PROCESSING APPARATUS 审中-公开
标题翻译：等离子体加工设备
公开(公告)号：US20130008608A1
公开(公告)日：2013-01-10
申请号：US13542068
申请日：2012-07-05
申请人： Naoki MATSUMOTO , Yasuhiro OTSUKA
发明人： Naoki MATSUMOTO , Yasuhiro OTSUKA
IPC分类号： H05H1/24 , B44C1/22
CPC分类号： H01J37/32642 , H01J37/32192 , H01L21/3065 , H01L21/31116
摘要： The plasma processing apparatus includes a processing container, a gas supplying unit, an introducing unit, a holding member, and a focus ring. In a processing space defined by the processing container, plasma of a processing gas supplied from the gas supplying unit is generated by energy introduced from the introducing unit. The holding member for holding an object to be processed and a focus ring formed to surround a cross-section of the holding member are disposed in the processing space. A gap equal to or less than 350 μm is defined between the cross-section of the holding member and the focus ring.
摘要翻译：等离子体处理装置包括处理容器，气体供给单元，引入单元，保持构件和聚焦环。在由处理容器限定的处理空间中，由从引入单元引入的能量产生从气体供给单元供给的处理气体的等离子体。用于保持待处理物体的保持构件和围绕保持构件的横截面形成的聚焦环设置在处理空间中。在保持构件和聚焦环的横截面之间限定等于或小于350μm的间隙。

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