专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08325543B2 Global bit select circuit interface with false write through blocking 有权
标题翻译：全局位选择电路接口通过阻塞伪写
公开(公告)号：US08325543B2
公开(公告)日：2012-12-04
申请号：US12713636
申请日：2010-02-26
申请人： Yuen Hung Chan , Antonia R. Pelella
发明人： Yuen Hung Chan , Antonia R. Pelella
IPC分类号： G11C19/08
CPC分类号： G11C7/18 , G11C7/12 , G11C8/14 , G11C11/413 , G11C2207/002
摘要： A global to local bit line interface circuit for domino SRAM devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through corresponding local write bit lines, the complementary global write bit lines configured to write a selected SRAM cell with data presented on a pair of complementary write data input lines; a pair of complementary global read bit lines in selective communication with the array of SRAM cells through corresponding local read bit lines, the complementary global read bit lines configured to read data stored in a selected SRAM cell and present the read data on a pair of complementary read data output lines; and blocking logic configured to prevent, during a write operation, propagation of stored data from the SRAM cells out on the complementary read data output lines prior to completion of the write operation.
摘要翻译：用于多米诺骨架SRAM器件的全局到本地位线接口电路包括一对互补的全局写入位线，其通过相应的本地写入位线与SRAM单元的阵列选择性地通信，所述互补的全局写入位线被配置为写入所选择的SRAM单元数据呈现在一对补充写入数据输入线上; 一对互补的全局读取位线，其通过对应的本地读取位线与SRAM单元的阵列选择性地通信，所述互补的全局读取位线被配置为读取存储在所选择的SRAM单元中的数据，并将读取的数据呈现在一对互补的读取数据输出行; 以及阻塞逻辑，其被配置为在写入操作期间，在写操作完成之前，将存储的数据从SRAM单元传播到互补读数据输出线上。

12. 发明申请

US20110211400A1 GLOBAL BIT SELECT CIRCUIT INTERFACE WITH FALSE WRITE THROUGH BLOCKING 有权
标题翻译：全局位选择通过阻塞写入错误的接口
公开(公告)号：US20110211400A1
公开(公告)日：2011-09-01
申请号：US12713636
申请日：2010-02-26
申请人： Yuen Hung Chan , Antonia R. Pelella
发明人： Yuen Hung Chan , Antonia R. Pelella
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C7/18 , G11C7/12 , G11C8/14 , G11C11/413 , G11C2207/002
摘要： A global to local bit line interface circuit for domino SRAM devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through corresponding local write bit lines, the complementary global write bit lines configured to write a selected SRAM cell with data presented on a pair of complementary write data input lines; a pair of complementary global read bit lines in selective communication with the array of SRAM cells through corresponding local read bit lines, the complementary global read bit lines configured to read data stored in a selected SRAM cell and present the read data on a pair of complementary read data output lines; and blocking logic configured to prevent, during a write operation, propagation of stored data from the SRAM cells out on the complementary read data output lines prior to completion of the write operation.
摘要翻译：用于多米诺骨架SRAM器件的全局到本地位线接口电路包括一对互补的全局写入位线，其通过相应的本地写入位线与SRAM单元的阵列选择性地通信，所述互补的全局写入位线被配置为写入所选择的SRAM单元数据呈现在一对补充写入数据输入线上; 一对互补的全局读取位线，其通过对应的本地读取位线与SRAM单元的阵列选择性地通信，所述互补的全局读取位线被配置为读取存储在所选择的SRAM单元中的数据，并将读取的数据呈现在一对互补的读取数据输出行; 以及阻塞逻辑，其被配置为在写入操作期间，在写操作完成之前，将存储的数据从SRAM单元传播到互补读数据输出线上。

13. 发明授权

US5783949A Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories 失效
公开(公告)号：US5783949A
公开(公告)日：1998-07-21
申请号：US518414
申请日：1995-08-24
申请人： William Robert Reohr , Yuen Hung Chan , Pong-Fei Lu
发明人： William Robert Reohr , Yuen Hung Chan , Pong-Fei Lu
IPC分类号： G11C11/41 , G11C7/06 , G11C8/10 , G11C11/419 , H01L21/822 , H01L27/04 , H01L27/10 , H03F3/45 , H03K19/003 , H03R19/0944
CPC分类号： G11C8/10 , G11C7/065
摘要： A memory and sense amplifier with latched output included therein derives high speed and noise immunity with precharged logic circuits through the separation of sense amplifier enablement and resetting by use of the precharge operation. Inclusion of bit line decoders which are wholly or partially self-resetting and self-precharging in sense amplifier support circuitry allows high performance at extremely short memory operation cycle times. A multiplexor is included which is usable in operating cycles as well as test cycles of the memory and further, in combination with other elements of the memory and sense amplifier arrangement, enables the pipelining of plural memory operations in a single memory cycle.

14. 发明授权

US5740412A Set-select multiplexer with an array built-in self-test feature 失效
标题翻译：具有阵列内置自检功能的集合选择多路复用器
公开(公告)号：US5740412A
公开(公告)日：1998-04-14
申请号：US642985
申请日：1996-05-06
申请人： Yuen Hung Chan , Pong-Fei Lu , Antonio Raffaele Pelella
发明人： Yuen Hung Chan , Pong-Fei Lu , Antonio Raffaele Pelella
IPC分类号： G06F12/08 , G06F12/10 , G11C29/50 , G16F1/04
CPC分类号： G11C29/50 , G06F12/0855 , G06F12/1054
摘要： A pipelined set-associative cache data READ/WRITE access circuit advancing the processing performance speeds in microprocessor memories. It provides an apparatus and method to obtain quick access to multi-way cache memory associates for both READ and WRITE operations satisfying the required increased memory access performance speeds for modern microprocessor utilizations. Special methodology is employed to minimize the number of pathways and the pathway through-time of the longest time critical path even with a provision of array built in self test (ABIST) capability.
摘要翻译：流水线相关高速缓存数据READ / WRITE访问电路提高了微处理器存储器中的处理性能速度。它提供了一种用于获得快速访问多路缓存存储器相关器的装置和方法，用于READ和WRITE操作，满足现代微处理器利用所需的增加的存储器访问性能速度。采用特殊的方法，即使提供内置自检（ABIST）能力的阵列，也可最大限度地减少最长时间关键路径的路径数和通路时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式