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11. 发明申请

US20060267216A1 INDUCTIVE FILTERS AND METHODS OF FABRICATION THEREFOR 有权
标题翻译：电感滤波器及其制造方法
公开(公告)号：US20060267216A1
公开(公告)日：2006-11-30
申请号：US11462611
申请日：2006-08-04
申请人： Yuan-Liang Li , David Figueroa
发明人： Yuan-Liang Li , David Figueroa
IPC分类号： H01L23/48
CPC分类号： H01F17/0033 , H01F41/041 , H01L23/49822 , H01L23/49838 , H01L2224/16 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/15312 , H05K1/115 , H05K1/165 , H05K3/06 , H05K3/42 , H05K2201/086 , H05K2201/097 , H05K2201/1006 , H05K2203/0723 , H01L2224/0401
摘要： A series of plated through hole (PTH) vias are interconnected by traces that alternate between a top surface and a bottom surface of a dielectric board. The PTH vias in the series can be positioned to create a collinear inductive filter, a coil-type inductive filter, or a transformer. Multiple, electrically isolated series of interconnected PTH vias can be used as a multi-phase inductive filter in one embodiment. In another embodiment, multiple series of interconnected PTH vias are electrically connected by a linking portion of conductive material, resulting in a low-resistance inductive filter. Ferromagnetic material patterns can be embedded in the dielectric board to enhance the inductive characteristics of the interconnected via structures. In one embodiment, a closed-end pattern is provided with two series of interconnected vias coiling around the pattern, resulting in an embedded transformer structure. A method of producing an interconnected series of PTH vias includes providing a dielectric board having a series of holes. In some embodiments, the board includes an embedded ferromagnetic material pattern. The holes and the top and bottom surface of the dielectric board have a conductive material thereupon. Portions of the conductive material are selectively removed, resulting in the embedded inductive filter and/or transformer structure.
摘要翻译：一系列电镀通孔（PTH）通孔在电介质板的顶表面和底表面之间交替的迹线互连。该系列中的PTH通孔可以定位成产生共线感应滤波器，线圈型感应滤波器或变压器。在一个实施例中，多个电隔离的互连PTH通孔系列可用作多相感应滤波器。在另一个实施例中，多个互连的PTH通孔系列通过导电材料的连接部分电连接，导致低电阻感应滤波器。铁磁材料图案可以嵌入电介质板中以增强互连通孔结构的感应特性。在一个实施例中，闭合端图案具有围绕图案卷绕的两系列互连的通孔，从而形成嵌入式变压器结构。制造互连的PTH通孔系列的方法包括提供具有一系列孔的电介质板。在一些实施例中，板包括嵌入的铁磁材料图案。电介质板的孔和顶表面和底表面具有导电材料。选择性地去除导电材料的部分，从而产生嵌入的感应滤波器和/或变压器结构。

12. 发明授权

US08468366B2 Method for securely storing a programmable identifier in a communication station 有权
标题翻译：用于在通信站中安全地存储可编程标识符的方法
公开(公告)号：US08468366B2
公开(公告)日：2013-06-18
申请号：US12054318
申请日：2008-03-24
申请人： David Figueroa , James A. Hutchison
发明人： David Figueroa , James A. Hutchison
IPC分类号： G06F21/00
CPC分类号： H04W12/12 , H04L63/0428 , H04L63/10
摘要： Disclosed is a method for storing an identifier in a first station having a secure non-volatile data store protected by cryptographic data, an identifier flag for indicating that the identifier has been written to the secure data store, and an authenticated trust agent that prohibits writing of an identifier to the secure data store if the identifier flag is set. In the method, the identifier is written to the secure non-volatile data store, wherein the identifier written to the secure data store is encrypted using the cryptographic data. The identifier flag is irreversibly set after writing the identifier to the secure data store so that the trust agent prohibits another write of an identifier to the secure data store.
摘要翻译：公开了一种用于在具有由密码数据保护的安全非易失性数据存储器的第一站中存储标识符的方法，用于指示标识符已被写入安全数据存储器的标识符标志以及禁止写入的认证信任代理的标识符到安全数据存储器，如果设置了标识符标志。在该方法中，将标识符写入安全非易失性数据存储器，其中使用密码数据对写入安全数据存储器的标识符进行加密。在将标识符写入安全数据存储器之后，标识符标志被不可逆地设置，使得信任代理禁止对安全数据存储器另外写入标识符。

13. 发明授权

US06558181B2 System and method for package socket with embedded power and ground planes 有权
公开(公告)号：US06558181B2
公开(公告)日：2003-05-06
申请号：US09751598
申请日：2000-12-29
申请人： Chee-Yee Chung , David Figueroa , Kris Frutschy , Bob Sankman , Farzaneh Yahyaei-Moayyed
发明人： Chee-Yee Chung , David Figueroa , Kris Frutschy , Bob Sankman , Farzaneh Yahyaei-Moayyed
IPC分类号： H01R13625
CPC分类号： H05K7/1092 , H05K1/0231 , H05K1/141 , Y10T29/49169
摘要： A system and method for embedding power and ground planes in a pin grid array (PGA) socket is provided. Integrated circuit pins are inserted into multiple insertion holes of varying dimensions in the power and ground planes. When the cover of the socket is slidably moved, power pins touch the power plane and ground pins touch the ground plane. Decoupling capacitors are also affixed to the substrate. Thus, the power delivery performance of the overall central processing unit (CPU) package is improved. Moreover, the power and ground planes enhance the mechanical strength of the socket which reduces warpage.

14. 发明申请

US20060279940A1 ELECTRONIC ASSEMBLIES COMPRISING CERAMIC/ORGANIC HYBRID SUBSTRATE WITH EMBEDDED CAPACITORS 失效
标题翻译：包含嵌入式电容器的陶瓷/有机混合基板的电子组件
公开(公告)号：US20060279940A1
公开(公告)日：2006-12-14
申请号：US11466351
申请日：2006-08-22
申请人： Kishore Chakravorty , Paul Wermer , David Figueroa , Debabrata Gupta
发明人： Kishore Chakravorty , Paul Wermer , David Figueroa , Debabrata Gupta
IPC分类号： H05K7/06 , H05K1/03
CPC分类号： H01L23/49822 , H01L23/50 , H01L2224/16225 , H01L2924/00014 , H01L2924/01004 , H01L2924/01077 , H01L2924/01078 , H01L2924/01087 , H01L2924/09701 , H01L2924/15174 , H01L2924/3011 , H01L2924/3511 , H05K1/0231 , H05K1/0306 , H05K1/141 , H05K1/162 , H05K1/185 , H05K3/4605 , H05K3/4688 , H05K2201/0154 , H05K2201/09309 , H05K2201/10674 , H01L2224/0401
摘要： To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.
摘要翻译：为了降低开关噪声，集成电路管芯的电源端子耦合到多层陶瓷/有机混合衬底中的至少一个嵌入式电容器的相应端子。在一个实施例中，衬底的陶瓷部分包括由夹在导电平面之间的高电容率层形成的至少一个电容器。基板的有机部分包括电源和信号导体的合适布线和扇出。有机部分包括覆盖陶瓷部分的多层有机材料的堆积。还描述了电子系统，数据处理系统和各种制造方法。

15. 发明授权

US06584685B2 System and method for package socket with embedded power and ground planes 有权
标题翻译：具有嵌入式电源和接地层的封装插座的系统和方法
公开(公告)号：US06584685B2
公开(公告)日：2003-07-01
申请号：US10025257
申请日：2001-12-17
申请人： Chee-Yee Chung , David Figueroa , Kris Frutschy , Bob Sankman , Farzaneh Yahyaei-Moayyed
发明人： Chee-Yee Chung , David Figueroa , Kris Frutschy , Bob Sankman , Farzaneh Yahyaei-Moayyed
IPC分类号： H05K1300
CPC分类号： H05K7/1092 , H05K1/0231 , H05K1/141 , Y10T29/49169
摘要： A system and method for embedding power and ground planes in a pin grid array (PGA) socket is provided. Integrated circuit pins are inserted into multiple insertion holes of varying dimensions in the power and ground planes. When the cover of the socket is slidably moved, power pins touch the power plane and ground pins touch the ground plane. Decoupling capacitors are also affixed to the substrate. Thus, the power delivery performance of the overall central processing unit (CPU) package is improved. Moreover, the power and ground planes enhance the mechanical strength of the socket which reduces warpage.
摘要翻译：提供了一种将电源和接地平面嵌入引脚格阵列（PGA）插座的系统和方法。集成电路引脚插入电源和接地层中不同尺寸的多个插入孔。当插座的盖子可滑动移动时，电源插头触摸电源平面，接地引脚接触地平面。去耦电容器也贴在基板上。因此，整体中央处理单元（CPU）封装的功率传递性能得到改善。此外，电源和接地平面增强了插座的机械强度，减少了翘曲。

16. 发明申请

US20090240954A1 METHOD FOR SECURELY STORING A PROGRAMMABLE IDENTIFIER IN A COMMUNICATION STATION 有权
标题翻译：在通信站中安全地存储可编程标识符的方法
公开(公告)号：US20090240954A1
公开(公告)日：2009-09-24
申请号：US12054318
申请日：2008-03-24
申请人： David Figueroa , James A. Hutchison
发明人： David Figueroa , James A. Hutchison
IPC分类号： H04L9/32
CPC分类号： H04W12/12 , H04L63/0428 , H04L63/10
摘要： Disclosed is a method for storing an identifier in a first station having a secure non-volatile data store protected by cryptographic data, an identifier flag for indicating that the identifier has been written to the secure data store, and an authenticated trust agent that prohibits writing of an identifier to the secure data store if the identifier flag is set. In the method, the identifier is written to the secure non-volatile data store, wherein the identifier written to the secure data store is encrypted using the cryptographic data. The identifier flag is irreversibly set after writing the identifier to the secure data store so that the trust agent prohibits another write of an identifier to the secure data store.
摘要翻译：公开了一种用于在具有由密码数据保护的安全非易失性数据存储器的第一站中存储标识符的方法，用于指示标识符已被写入安全数据存储器的标识符标志以及禁止写入的认证信任代理的标识符到安全数据存储器，如果设置了标识符标志。在该方法中，将标识符写入安全非易失性数据存储器，其中使用密码数据对写入安全数据存储器的标识符进行加密。在将标识符写入安全数据存储器之后，标识符标志被不可逆地设置，使得信任代理禁止对安全数据存储器另外写入标识符。

17. 发明申请

US20080263117A1 INITIAL SEED MANAGEMENT FOR PSEUDORANDOM NUMBER GENERATOR 审中-公开
标题翻译： PSEUDORANDOM NUMBER GENERATOR的初步种子管理
公开(公告)号：US20080263117A1
公开(公告)日：2008-10-23
申请号：US11738972
申请日：2007-04-23
申请人： Gregory Gordon Rose , Alexander Gantman , Lu Xiao , David Figueroa
发明人： Gregory Gordon Rose , Alexander Gantman , Lu Xiao , David Figueroa
IPC分类号： G06F7/58 , G06F15/177
CPC分类号： G06F7/582 , G06F7/588 , H04L9/0869
摘要： A secure seeding and reseeding scheme is provided for pseudorandom number generators by using a pre-stored initialization seed. This scheme initializes a pseudorandom number generator into an unknown state even when entropy collection is unavailable. A primary seed file and a shadow seed file are maintained with initialization seed information in a secure file system. If the primary seed file is corrupted, the pseudorandom number generator is seeded with the content of the shadow seed file. Additionally, a trusted timer or clock may be mixed with the pre-stored initialization seed to add entropy even when the pre-stored seed information has been compromised.
摘要翻译：通过使用预先存储的初始化种子为伪随机数发生器提供安全的种子和再种植方案。即使熵收集不可用，该方案将伪随机数发生器初始化为未知状态。在安全文件系统中，使用初始化种子信息维护主种子文件和影子种子文件。如果主种子文件被破坏，则伪随机数生成器被种子与影子种子文件的内容。此外，即使预先存储的种子信息已被破坏，可信任的定时器或时钟可以与预先存储的初始化种子混合以添加熵。

18. 发明申请

US20070150197A1 Method to control delay between lanes 有权
标题翻译：控制车道延误的方法
公开(公告)号：US20070150197A1
公开(公告)日：2007-06-28
申请号：US11322059
申请日：2005-12-28
申请人： Srikrishnan Venkataraman , Jayashree Kar , Sudarshan Solanki , P. Patel , Michael DeSmith , David Figueroa
发明人： Srikrishnan Venkataraman , Jayashree Kar , Sudarshan Solanki , P. Patel , Michael DeSmith , David Figueroa
IPC分类号： G08G1/16
CPC分类号： G06F13/4004
摘要： Method and apparatus to control delay between lanes in an I/O interface is disclosed. To control the delay between the lanes in the I/O system a programmed delay may be determined and introduced between the lanes. For this purpose the effective time “T” of the lanes is determined. The number of lanes “N” in the I/O interface is identified. The programmed lane to lane delay “D” is determined and a delay circuit having the programmed delay may be introduced between the lanes to reduce AC peak to peak noise in the I/O system.
摘要翻译：公开了一种用于控制I / O接口中的通道之间的延迟的方法和装置。为了控制I / O系统中的通道之间的延迟，可以确定并在车道之间引入编程的延迟。为此，确定车道的有效时间“T”。识别I / O接口中的通道数“N”。确定经编程的车道延迟“D”，并且可以在车道之间引入具有编程延迟的延迟电路，以减少I / O系统中的AC峰峰值噪声。

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