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11. 发明申请

US20100244244A1 Chip Having a Bump and Package Having the Same 有权
标题翻译：具有颠簸和封装的芯片具有相同的功能
公开(公告)号：US20100244244A1
公开(公告)日：2010-09-30
申请号：US12726777
申请日：2010-03-18
申请人： Kuo-Pin Yang
发明人： Kuo-Pin Yang
IPC分类号： H01L23/498
CPC分类号： H01L23/49816 , H01L23/481 , H01L23/49827 , H01L24/12 , H01L24/16 , H01L25/0657 , H01L2224/0401 , H01L2224/0557 , H01L2224/05572 , H01L2224/13023 , H01L2224/13025 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16235 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00013 , H01L2924/0002 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/00014 , H01L2224/13099 , H01L2224/05552
摘要： The present invention relates to a chip having a bump and a package having the same. The chip includes a chip body, at least one via, a passivation layer, an under ball metal layer and at least one bump. The via penetrates the chip body, and is exposed to a surface of the chip body. The passivation layer is disposed on the surface of the chip body, and the passivation layer has at least one opening. The opening exposes the via. The under ball metal layer is disposed in the opening of the passivation layer, and is connected to the via. The bump is disposed on the under ball metal layer, and includes a first metal layer, a second metal layer and a third metal layer. The first metal layer is disposed on the under ball metal layer. The second metal layer is disposed on the first metal layer. The third metal layer is disposed on the second metal layer. As the bumps can connect two chips, the chip is stackable, and so the density of the product is increased while the size of the product is reduced.
摘要翻译：本发明涉及具有凸块的芯片和具有该凸块的封装。芯片包括芯片体，至少一个通孔，钝化层，下部球金属层和至少一个凸块。通孔穿透芯片体并暴露于芯片体的表面。钝化层设置在芯片体的表面上，钝化层具有至少一个开口。开幕式暴露了通道。下球金属层设置在钝化层的开口中，并连接到通孔。凸块设置在下球金属层上，并且包括第一金属层，第二金属层和第三金属层。第一金属层设置在球形金属层的下方。第二金属层设置在第一金属层上。第三金属层设置在第二金属层上。由于凸块可以连接两个芯片，芯片可堆叠，因此产品的密度增加，而产品的尺寸减小。

12. 发明申请

US20070252261A1 SEMICONDUCTOR DEVICE PACKAGE 审中-公开
标题翻译：半导体器件封装
公开(公告)号：US20070252261A1
公开(公告)日：2007-11-01
申请号：US11612457
申请日：2006-12-18
申请人： Meng-Jen Wang , Kuo-Pin Yang , Sheng-Yang Peng , Wei-Min Hsiao
发明人： Meng-Jen Wang , Kuo-Pin Yang , Sheng-Yang Peng , Wei-Min Hsiao
IPC分类号： H01L23/02
CPC分类号： H01L23/04 , B81B7/0077 , H01L24/48 , H01L25/03 , H01L25/0657 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06575 , H01L2924/00014 , H01L2924/14 , H01L2924/1461 , H01L2924/16151 , H01L2924/19105 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a semiconductor device package, comprising a carrier, a first semiconductor device, a second semiconductor device, a plurality of conductive elements, a pre-mold and a lid. The first semiconductor device is electrically connected to the carrier. The second semiconductor device is disposed above the first semiconductor device. The conductive elements are used for electrically connecting the second semiconductor device and the carrier. The pre-mold and the carrier form an accommodating space for accommodating the first semiconductor device, the second semiconductor device and the conductive elements. The lid is adhered to the pre-mold for covering the opening of the pre-mold. As a result, the pre-mold is formed by molding, the manufacture process of the present invention is simpler than that of the conventional semiconductor device package.
摘要翻译：本发明涉及一种半导体器件封装，包括载体，第一半导体器件，第二半导体器件，多个导电元件，预模具和盖子。第一半导体器件电连接到载体。第二半导体器件设置在第一半导体器件的上方。导电元件用于电连接第二半导体器件和载体。预模具和载体形成用于容纳第一半导体器件，第二半导体器件和导电元件的容纳空间。盖子粘附到预模具以覆盖预模具的开口。结果，通过模制形成预模具，本发明的制造工艺比传统的半导体器件封装简单。

13. 发明申请

US20060255253A1 Method for packaging an image sensor die and a package thereof 审中-公开
标题翻译：包装图像传感器芯片及其封装的方法
公开(公告)号：US20060255253A1
公开(公告)日：2006-11-16
申请号：US11287269
申请日：2005-11-28
申请人： Wei-Min Hsiao , Kuo-Pin Yang
发明人： Wei-Min Hsiao , Kuo-Pin Yang
IPC分类号： H01J5/02
CPC分类号： H01L27/14618 , H01L27/14683 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/16195 , H01L2924/00014 , H01L2924/00
摘要： A method and package for packaging an image sensor die utilizes a substrate having a concave space and an opening to connect the image sensor die with the substrate by SMT method. This method can reduce the manufacturing process of packaging the image sensor. The packaging method comprises providing a wafer having a plurality of image sensors, sawing the wafer to form a plurality of dies with a single image sensor, electrically connecting the die having the image sensor with a substrate, the substrate comprising a concave space and an opening, a plurality of solder pads disposed in the concave space for electrically connecting the die having an image sensor, and a plurality of input/output solder pads on the same side of the substrate for connecting to an external element, and filling a transparent adhesive into the opening of the substrate.
摘要翻译：用于封装图像传感器芯片的方法和封装利用具有凹形空间和开口的基板，通过SMT方法将图像传感器裸片与基板连接。这种方法可以减少包装图像传感器的制造过程。包装方法包括提供具有多个图像传感器的晶片，锯切晶片以形成具有单个图像传感器的多个管芯，将具有图像传感器的管芯与基板电连接，该基板包括凹形空间和开口设置在所述凹形空间中的多个焊盘，用于电连接具有图像传感器的管芯，以及在所述衬底的同一侧上的多个输入/输出焊盘，用于连接到外部元件，并且将透明粘合剂填充到基板的开口。

14. 发明授权

US06150730A Chip-scale semiconductor package 有权
标题翻译：芯片级半导体封装
公开(公告)号：US06150730A
公开(公告)日：2000-11-21
申请号：US349231
申请日：1999-07-08
申请人： Chih-Ming Chung , Kuo-Pin Yang , Jen-Kuang Fang , Su Tao
发明人： Chih-Ming Chung , Kuo-Pin Yang , Jen-Kuang Fang , Su Tao
IPC分类号： H01L23/495 , H01L23/498 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/4951 , H01L23/49816 , H01L23/49827 , H01L24/50 , H01L2924/14
摘要： A chip-scale semiconductor package mainly includes a semiconductor chip, a substrate and a package body. Said chip is attached onto said substrate by an adhesive layer. Said chip has a plurality of bonding pads formed thereon. Said adhesive layer has an aperture corresponding to the bonding pads of said chip such that the bonding pads can be exposed within an aperture. Said substrate has several through-holes respectively corresponding to the bonding pads of said chip and parts of the area around the edge of said chip for dispensing of encapsulant after the soldering of leads of said substrate to the bonding pads of said chip. The encapsulant dispensed into the through-holes can flow from the surface of said chip to the edge thereof. Said package body has one portion provided within the through-hole of said substrate and another portion provided around the edge of said chip whereby encapsulation process is accomplished without having to turn the whole semiconductor package device.
摘要翻译：芯片级半导体封装主要包括半导体芯片，基板和封装体。所述芯片通过粘合剂层附着在所述基板上。所述芯片具有形成在其上的多个接合焊盘。所述粘合剂层具有对应于所述芯片的焊盘的孔，使得焊盘可以暴露在孔内。所述衬底具有分别对应于所述芯片的焊盘和所述芯片的边缘周围区域的部分的多个通孔，用于在将所述衬底的引线焊接到所述芯片的焊盘之后分配密封剂。分配到通孔中的密封剂可以从所述芯片的表面流动到其边缘。所述封装体具有设置在所述基板的通孔内的一部分和设置在所述芯片的边缘周围的另一部分，从而实现封装处理而不必转动整个半导体封装器件。

15. 发明申请

US20120175767A1 SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIAS AND METHOD FOR MAKING THE SAME 有权
标题翻译：具有通孔硅的半导体封装及其制造方法
公开(公告)号：US20120175767A1
公开(公告)日：2012-07-12
申请号：US13311364
申请日：2011-12-05
申请人： Chia-Lin Hung , Jen-Chuan Chen , Hui-Shan Chang , Kuo-Pin Yang
发明人： Chia-Lin Hung , Jen-Chuan Chen , Hui-Shan Chang , Kuo-Pin Yang
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L24/14 , H01L21/6836 , H01L23/3128 , H01L23/481 , H01L23/49816 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2221/68331 , H01L2224/0401 , H01L2224/05025 , H01L2224/05155 , H01L2224/0557 , H01L2224/05644 , H01L2224/05655 , H01L2224/13009 , H01L2224/13025 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/14181 , H01L2224/16148 , H01L2224/16238 , H01L2224/29036 , H01L2224/2919 , H01L2224/33181 , H01L2224/73204 , H01L2224/81193 , H01L2224/8121 , H01L2224/81815 , H01L2224/83192 , H01L2224/92125 , H01L2224/92225 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01029 , H01L2924/15311 , H01L2924/181 , H01L2924/3511 , H01L2924/0665 , H01L2924/01047 , H01L2224/81 , H01L2224/80213 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： The present invention relates to a stacked semiconductor package and a method for making the same. The method includes the steps of mounting a plurality of first dice to a wafer by conducting a reflow process; and thinning the wafer from the backside surface of the wafer, thereby reducing manufacturing time and preventing warpage.
摘要翻译：本发明涉及堆叠式半导体封装及其制造方法。该方法包括通过进行回流处理将多个第一骰子安装到晶片的步骤; 并且从晶片的背面使晶片变薄，从而减少制造时间并防止翘曲。

16. 发明申请

US20100187681A1 Silicon Substrate Having Through Vias and Package Having the Same 有权
标题翻译：具有透明度的硅基板和具有相同的封装
公开(公告)号：US20100187681A1
公开(公告)日：2010-07-29
申请号：US12691478
申请日：2010-01-21
申请人： Kuo-Hua Chen , Kuo-Pin Yang
发明人： Kuo-Hua Chen , Kuo-Pin Yang
IPC分类号： H01L23/34 , H01L23/48
CPC分类号： H01L23/49827 , H01L23/147 , H01L23/3677 , H01L23/49816 , H01L24/16 , H01L25/0652 , H01L2224/16 , H01L2224/16225 , H01L2224/16235 , H01L2225/06517 , H01L2225/0652 , H01L2225/06572 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： The present invention relates to a silicon substrate having through vias and a package having the same. The silicon substrate includes a substrate body, a plurality of through vias and at least one heat dissipating area. The substrate body has a surface, and the material of the substrate body is silicon. The through vias penetrate the substrate body, and each of the through vias has a conductive material therein. The heat dissipating area is disposed on the surface of the substrate body and covers at least two through vias. The heat dissipating area is made of metal, and the through vias inside the heat dissipating area have same electrical potential. Thus, the heat in the through vias is transmitted to the heat dissipating area, and since the area of the heat dissipating area is large, the silicon substrate has good heat dissipation efficiency.
摘要翻译：本发明涉及具有通孔的硅衬底和具有该通孔的封装。硅衬底包括衬底主体，多个通孔和至少一个散热区域。基板主体具有表面，并且基板主体的材料是硅。通孔穿透基板主体，并且通孔中的每一个在其中具有导电材料。散热区域设置在基板主体的表面上并且覆盖至少两个通孔。散热区由金属制成，散热区内的通孔具有相同的电位。因此，通孔中的热量传递到散热区域，由于散热面积大，所以硅基板具有良好的散热效率。

17. 发明授权

US07573124B2 Semiconductor packaging structure having electromagnetic shielding function and method for manufacturing the same 有权
标题翻译：具有电磁屏蔽功能的半导体封装结构及其制造方法
公开(公告)号：US07573124B2
公开(公告)日：2009-08-11
申请号：US11772243
申请日：2007-07-02
申请人： Meng-Jen Wang , Kuo-Pin Yang , Wei-Min Hsiao , Sheng-Yang Peng
发明人： Meng-Jen Wang , Kuo-Pin Yang , Wei-Min Hsiao , Sheng-Yang Peng
IPC分类号： H01L23/552
CPC分类号： H01L23/552 , B81B7/0064 , B81B2201/0257 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/02166 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49107 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/14 , H01L2924/3025 , H01L2924/00014
摘要： A semiconductor packaging structure having electromagnetic shielding function is disclosed, in which the packaging structure includes a carrier and a semiconductor substrate disposed thereon. The semiconductor substrate has a patterned passivation layer and a patterned metal layer disposed thereon, in which the patterned metal layer is electrically connected to at least a grounding pad of the carrier via a wire, whereby possessing the semiconductor packaging structure to have electromagnetic shielding function. A method for manufacturing a semiconductor packaging structure having electromagnetic shielding function is also disclosed in the present invention.
摘要翻译：公开了一种具有电磁屏蔽功能的半导体封装结构，其中封装结构包括载体和设置在其上的半导体衬底。半导体衬底具有图案化的钝化层和设置在其上的图案化金属层，其中图案化的金属层经由导线电连接到载体的至少接地焊盘，由此具有半导体封装结构以具有电磁屏蔽功能。本发明还公开了一种具有电磁屏蔽功能的半导体封装结构的制造方法。

18. 发明授权

US07435621B2 Method of fabricating wafer level package 有权
标题翻译：制造晶圆级封装的方法
公开(公告)号：US07435621B2
公开(公告)日：2008-10-14
申请号：US11416078
申请日：2006-05-03
申请人： Kuo-Pin Yang
发明人： Kuo-Pin Yang
IPC分类号： H01L21/00
CPC分类号： H01L23/3114 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating wafer level package is provided. First, a wafer having a front and a rear surfaces is provided. Several fosses are then formed on the front surface of the wafer. Next, an insulative layer is formed on a surface of each fosse; a conductive layer is then formed on part of the front surface of the wafer and the insulative layer of each fosse. A solder layer is formed on the conductive layer above each fosse. Afterward, a first substrate is attached to the front surface. Several holes are formed on the rear surface, and the holes baring the solder layer are positioned corresponding to the fosses. Then, a second substrate is attached to the rear surface of the wafer. The second substrate has several conductive pillars correspondingly inserted into the holes for connecting the solder layers. Next, the conductive structures are formed on the second substrate.
摘要翻译：提供了制造晶片级封装的方法。首先，提供具有前表面和后表面的晶片。然后在晶片的前表面上形成几个藓类。接下来，在每个顶部的表面上形成绝缘层; 然后在晶片的前表面的一部分和每个晶片的绝缘层上形成导电层。在每个顶部上的导电层上形成焊料层。之后，将第一基板安装到前表面。在后表面上形成几个孔，并且对应于釉料定位焊接焊料层的孔。然后，将第二基板安装在晶片的后表面。第二基板具有相应地插入到用于连接焊料层的孔中的几个导电柱。接下来，在第二基板上形成导电结构。

19. 发明授权

US07429499B2 Method of fabricating wafer level package 有权
标题翻译：制造晶圆级封装的方法
公开(公告)号：US07429499B2
公开(公告)日：2008-09-30
申请号：US11292541
申请日：2005-12-02
申请人： Kuo-Pin Yang
发明人： Kuo-Pin Yang
IPC分类号： H01L21/00
CPC分类号： H01L23/3114 , H01L21/561 , H01L21/568 , H01L2221/6834 , H01L2224/13 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： A method of fabricating wafer level package is provided. The method includes the following steps. Firstly, a wafer having a front surface and a rear surface is provided, and the front surface has several conductive pads. Next, a supporting material is attached on the front surface. Then, several holes are formed on the wafer, and the holes run from the rear surface to the front surface. A first substrate is attached on the rear surface. The first substrate has several conductive pillars correspondingly inserted into the holes. Afterwards, the supporting material is removed to expose the conductive pillars on the front surface, and a patterned circuit is formed on the front surface. Next, a second substrate is attached on the patterned circuit. Then, several conductive structures are formed on the first substrate.
摘要翻译：提供了制造晶片级封装的方法。该方法包括以下步骤。首先，设置具有前表面和后表面的晶片，并且前表面具有多个导电焊盘。接下来，在前表面上安装支撑材料。然后，在晶片上形成多个孔，并且孔从后表面延伸到前表面。第一衬底附接在后表面上。第一衬底具有相应地插入孔中的几个导电柱。之后，去除支撑材料以露出前表面上的导电柱，并且在前表面上形成图案化电路。接下来，第二基板附着在图案化电路上。然后，在第一基板上形成多个导电结构。

20. 发明授权

US07238590B2 Package structure of semiconductor and wafer-level formation thereof 有权
标题翻译：半导体封装结构及其晶圆级形成
公开(公告)号：US07238590B2
公开(公告)日：2007-07-03
申请号：US11164818
申请日：2005-12-07
申请人： Kuo-Pin Yang , Wei-Min Hsiao
发明人： Kuo-Pin Yang , Wei-Min Hsiao
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L27/14618 , B81C1/0023 , B81C2203/0118 , H01L27/14632 , H01L27/14687 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16235 , H01L2224/16237 , H01L2224/81141 , H01L2224/81191 , H01L2224/9202 , H01L2924/00014 , H01L2924/1461 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： In wafer-level formation of a package structure of semiconductor, multitudes of conductive connection structures are formed protruded from a transparent substrate. Multitudes of grooves are formed in a semiconductor wafer and an adhesive is filled therein. The wafer and the transparent substrate are jointed in which each of the conductive connection structures are positioned in one of the grooves and exposed outside of another surface of the semiconductor wafer. A package structure is obtained by sawing the wafer and has electrical connection between the signals of the active side and back side through the conductive connection structures.
摘要翻译：在半导体的封装结构的晶片级形成中，形成从透明基板突出的多个导电连接结构。在半导体晶片中形成多个槽，并且在其中填充粘合剂。晶片和透明基板接合，其中每个导电连接结构位于一个凹槽中并暴露在半导体晶片的另一个表面的外部。通过锯切晶片获得封装结构，并且通过导电连接结构在有源侧和后侧的信号之间具有电连接。

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