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    • 17. 发明申请
    • Adaptive motion estimation and mode decision apparatus and method for H.264 video codec
    • H.264视频编解码器的自适应运动估计和模式决策设备及方法
    • US20060039470A1
    • 2006-02-23
    • US10976781
    • 2004-11-01
    • Yong-Hwan KimJe-Woo KimHyeok-Koo JungJoonki Paik
    • Yong-Hwan KimJe-Woo KimHyeok-Koo JungJoonki Paik
    • H04N11/02H04N7/12H04N11/04H04B1/66
    • H04N19/567H04N5/145H04N19/57
    • Disclosed herein is an adaptive motion estimation and mode decision apparatus and method for an H.264 video codec. The apparatus includes a background image detection unit, an inter mode inspection unit, an intra mode inspection unit and a mode inspection skip unit. The background image detection unit inspects whether a fixed background or slowly and regularly moving block exists, and skips the step of dividing a first corresponding macroblock into smaller sized blocks and performing block mode inspection. The inter mode inspection unit inspects whether an irregularly or fast moving macroblock exists, and determines whether to divide a corresponding macroblock into smaller sized blocks and to perform block mode inspection on the smaller sized blocks. The intra mode inspection unit performs AZCB inspection on the macroblocks, and determines whether to divide a corresponding macroblock into smaller sized blocks block and to perform mode inspection on the smaller sized blocks. The mode inspection skip unit skips the block mode inspection for the smaller sized blocks.
    • 这里公开了一种用于H.264视频编解码器的自适应运动估计和模式决定装置和方法。 该装置包括背景图像检测单元,帧间模式检查单元,帧内模式检查单元和模式检查跳过单元。 背景图像检测单元检查是否存在固定的背景或缓慢且有规律的移动块,并且跳过将第一对应宏块划分成较小尺寸块并执行块模式检查的步骤。 帧间模式检查单元检查是否存在不规则或快速移动的宏块,并且确定是否将相应的宏块划分成较小尺寸的块并且对较小尺寸的块执行块模式检查。 帧内模式检查单元对宏块执行AZCB检查,并且确定是否将对应的宏块分割成较小尺寸的块块,并对较小尺寸的块执行模式检查。 模式检查跳过单元跳过较小尺寸块的块模式检查。
    • 18. 发明授权
    • High voltage generating circuit
    • 高压发生电路
    • US06545529B2
    • 2003-04-08
    • US09843944
    • 2001-04-30
    • Yong-Hwan Kim
    • Yong-Hwan Kim
    • G05F110
    • H02M3/073H02M2003/075
    • A voltage generating circuit in accordance with the present invention includes a plurality of pump stages for alternatingly performing its pumping and pre-charging operation, and a pre-charge stage for pre-charging a first pump stage to a first reference voltage level (e.g., a power supply level). Each of the pump stages can include first and second pumps with a symmetrical structure for alternatingly performing a pumping operation and a pre-charging operation during a first clock cycle, and a charge transfer switch. The charge transfer switch is connected between the pumping capacitors of the first and second pumps, for thereby sharing the charge of each pumping capacitor of the first and second pumps before the first clock cycle is finished.
    • 根据本发明的电压产生电路包括用于交替执行其泵送和预充电操作的多个泵级,以及用于将第一泵级预充电到第一参考电压电平的预充电级(例如, 电源电平)。 每个泵级可以包括具有对称结构的第一和第二泵,用于在第一时钟周期期间交替执行泵送操作和预充电操作,以及电荷转移开关。 电荷转移开关连接在第一和第二泵的泵送电容器之间,从而在第一时钟周期完成之前共享第一和第二泵的每个泵送电容器的电荷。
    • 19. 发明授权
    • Variable length decoder with enhanced routing of data to multiplexers
    • 可变长度解码器,具有增强的数据路由到多路复用器
    • US6133860A
    • 2000-10-17
    • US186637
    • 1998-11-06
    • Seung-Chol RyuYong-Hwan Kim
    • Seung-Chol RyuYong-Hwan Kim
    • H04N19/00H03M7/40H04N1/41H04N19/423H04N19/426H04N19/91
    • H03M7/40
    • The present invention relates to a variable length decoder having a reduced size of a chip achieved by decreasing the size of the output data and simultaneously enabling effective input/output data processing. The present invention includes: a control signal generator for generating a data access control signal, a multiplexing control signal and a shift control signal wherein the control signal generator is supplied with the word length of data to be outputted; a first data storage device wherein a shift of a previously-stored data is executed when the data access control signal is activated and new data is inputted into a space vacated by the shift; a multiplexing device for outputting selectively a portion of data stored in the first data storage device according to the multiplexing control signal; and a shifter for varying a shift pointer according to a value of the shift control and for operating upon data from the multiplexing device.
    • 本发明涉及通过减小输出数据的大小并同时实现有效的输入/输出数据处理而实现的芯片尺寸减小的可变长度解码器。 本发明包括:用于产生数据访问控制信号的控制信号发生器,复用控制信号和移位控制信号,其中向控制信号发生器提供要输出的数据的字长; 第一数据存储装置,其中当数据访问控制信号被激活并且新数据被输入到由该移位空出的空间中时,执行先前存储的数据的移位; 多路复用装置,用于根据复用控制信号选择性地输出存储在第一数据存储装置中的数据的一部分; 以及移位器,用于根据移位控制的值改变移位指针,并对来自多路复用装置的数据进行操作。