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11. 发明授权

US06713821B2 Structure of a mask ROM device 有权
标题翻译：掩模ROM器件的结构
公开(公告)号：US06713821B2
公开(公告)日：2004-03-30
申请号：US10155619
申请日：2002-05-24
申请人： Tso-Hung Fan , Mu-Yi Liu , Kwang-Yang Chan , Yen-Hung Yeh , Tao-Cheng Lu
发明人： Tso-Hung Fan , Mu-Yi Liu , Kwang-Yang Chan , Yen-Hung Yeh , Tao-Cheng Lu
IPC分类号： H01L31062
CPC分类号： H01L27/1126 , H01L27/112
摘要： A mask ROM device is described. The mask ROM device includes a substrate, a gate, a double diffused source/drain region that comprises a first doped region and a second doped region, a channel region, a coding region, a dielectric layer and a word line. The gate is disposed on the substrate. The double diffused source/drain region is positioned beside the sides of the gate in the substrate, wherein the second doped region is located at the periphery of the first doped region in the substrate. The channel region is located between the double diffused source/drain region in the substrate. The coding region is disposed in the substrate at the intersection between the sides of the channel region and the double diffused source/drain region. The dielectric layer is disposed above the double diffused source/drain region, while the word line is disposed above the dielectric layer and the gate.
摘要翻译：描述掩模ROM设备。掩模ROM器件包括衬底，栅极，包括第一掺杂区域和第二掺杂区域的双扩散源极/漏极区域，沟道区域，编码区域，电介质层和字线。栅极设置在基板上。双扩散源极/漏极区域位于衬底中的栅极的侧面旁边，其中第二掺杂区域位于衬底中的第一掺杂区域的外围。沟道区位于衬底中的双扩散源极/漏极区之间。编码区域设置在沟道区域和双扩散源极/漏极区域的相交处的衬底中。电介质层设置在双扩散源极/漏极区域的上方，而字线设置在电介质层和栅极之上。

12. 发明授权

US06590266B1 2-bit mask ROM device and fabrication method thereof 有权
标题翻译： 2位掩模ROM器件及其制造方法
公开(公告)号：US06590266B1
公开(公告)日：2003-07-08
申请号：US10064906
申请日：2002-08-28
申请人： Mu-Yi Liu , Tso-Hung Fan , Kwang-Yang Chan , Yen-Hung Yeh , Tao-Cheng Lu
发明人： Mu-Yi Liu , Tso-Hung Fan , Kwang-Yang Chan , Yen-Hung Yeh , Tao-Cheng Lu
IPC分类号： H01L2994
CPC分类号： H01L27/11266 , H01L27/112
摘要： A 2-bit mask ROM device and a fabrication method thereof are described. The 2-bit mask ROM device includes a substrate; a gate structure, disposed on a part of the substrate; a 2-bit code region, configured in the substrate beside both sides of the gate structure; at least one spacer, disposed on both sides of the gate structure; a buried drain region, configured in the substrate beside both sides of the spacer; a doped region, configured in the substrate between the buried drain region and the 2-bit code region, wherein the dopant type of the doped region is different from that for the 2-bit code region and the dopant concentration in the doped region is higher than that in the 2-bit code region; an insulation layer, disposed above the buried drain region; and a word line disposed on the gate structures along a same row.
摘要翻译：描述2位掩模ROM器件及其制造方法。 2位掩模ROM器件包括衬底; 栅极结构，设置在所述衬底的一部分上; 2位代码区，配置在栅极结构的两侧旁边的基板中; 设置在所述栅极结构的两侧的至少一个间隔物; 掩埋漏极区域，被构造在所述衬底旁边的所述间隔物的两侧; 掺杂区域，配置在掩埋漏极区域和2位码区域之间的衬底中，其中掺杂区域的掺杂剂类型与2位码区域的掺杂区域不同，并且掺杂区域中的掺杂剂浓度更高比在2位代码区域; 绝缘层，设置在所述掩埋漏极区域的上方; 以及沿同一行设置在栅极结构上的字线。

13. 发明申请

US20060044718A1 Electrostatic discharge conduction device and mixed power integrated circuits using same 有权
标题翻译：静电放电传导器件和混合功率集成电路使用相同
公开(公告)号：US20060044718A1
公开(公告)日：2006-03-02
申请号：US10933181
申请日：2004-09-02
申请人： Shin Su , Chun-Hsiang Lai , Cha-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
发明人： Shin Su , Chun-Hsiang Lai , Cha-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
IPC分类号： H02H9/00
CPC分类号： H01L27/0251 , H01L27/0292
摘要： A device for connection between supply buses in mixed power integrated circuits includes a diode in series with a transistor with an active p-ring in a semiconductor substrate. The active p-ring surrounds the source and drain of the transistor with a conductive region having the same conductivity type as the semiconductor substrate. A control circuit coupled to the p-ring applies a bias voltage in response to an ESD event affecting the first and second conductors. The bias voltage tends to inject carriers into the semiconductor substrate which enables discharge of the short voltage pulse via a parasitic SCR in the substrate from the anode of the diode to the source of the transistor.
摘要翻译：用于在混合功率集成电路中的电源总线之间连接的装置包括与在半导体衬底中具有有源p型环的晶体管串联的二极管。有源P环围绕具有与半导体衬底相同导电类型的导电区域的晶体管的源极和漏极。耦合到p型环的控制电路响应于影响第一和第二导体的ESD事件施加偏置电压。偏置电压倾向于将载流子注入到半导体衬底中，其能够通过衬底中的寄生SCR从二极管的阳极到晶体管的源极放电短电压脉冲。

14. 发明授权

US07573102B2 ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad 有权
标题翻译： ESD保护结构和方法利用高耐压焊盘的基板触发
公开(公告)号：US07573102B2
公开(公告)日：2009-08-11
申请号：US11496490
申请日：2006-08-01
申请人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Yen-Hung Yeh , Chia-Ling Lu , Tao-Cheng Lu
发明人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Yen-Hung Yeh , Chia-Ling Lu , Tao-Cheng Lu
IPC分类号： H01L29/72
CPC分类号： H01L27/0266
摘要： In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.
摘要翻译：在ESD保护结构和方法中，利用衬底触发用于衬底上的高耐压焊盘，ESD保护器件具有连接到焊盘的源极和连接到地的栅极和漏极，以及衬底触发控制电路用于在正常操作期间将衬底保持在低电压，并且在ESD事件期间将衬底泵送到高电压以使ESD保护器件被触发得更容易。基板触发控制电路由有源器件实现，从而减小电路的芯片尺寸和对焊盘的负载效应。

15. 发明授权

US07012305B2 Electro-static discharge protection circuit for dual-polarity input/output pad 有权
标题翻译：用于双极输入/输出板的静电放电保护电路
公开(公告)号：US07012305B2
公开(公告)日：2006-03-14
申请号：US10708171
申请日：2004-02-12
申请人： Shin Su , Chun-Hsiang Lai , Chia-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
发明人： Shin Su , Chun-Hsiang Lai , Chia-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
IPC分类号： H01L23/62
CPC分类号： H01L27/0262 , H01L29/7436
摘要： An electro-static discharge (ESD) protection circuit for a dual polarity I/O pad is provided. The protection circuit includes a substrate of first type; a deep well region of second type disposed in the first type substrate; a well region of first type disposed in the second type deep well region; a first transistor disposed over the well region of first type, wherein the first transistor has a first source, a first gate and a first drain; a second transistor disposed over the substrate of first type, wherein the second transistor has a second source, a second gate and a second drain, and the second source is connected with the first drain, and both of them are disposed in a portion of the well region of first type, the deep well region of second type and the substrate of first type; a first doped region is disposed in the first type well region and laterally adjacent to the first source; a second doped region is disposed in the substrate of first type and laterally adjacent to the second drain.
摘要翻译：提供用于双极性I / O焊盘的静电放电（ESD）保护电路。保护电路包括第一类型的衬底; 设置在所述第一类型基板中的第二类型的深阱区域; 设置在第二类型深井区域中的第一类型井区域; 第一晶体管设置在第一类型的阱区上，其中第一晶体管具有第一源极，第一栅极和第一漏极; 设置在第一类型的衬底上的第二晶体管，其中第二晶体管具有第二源极，第二栅极和第二漏极，并且第二源极与第一漏极连接，并且它们都被布置在第一类井区，第二类深井区和第一类的基底; 第一掺杂区域设置在第一类型阱区域中并且横向邻近于第一源极; 第二掺杂区域设置在第一类型的衬底中并且横向邻近于第二漏极。

16. 发明申请

US20050269641A1 ELECTROSTATIC PROTECTION CIRCUIT 有权
标题翻译：静电保护电路
公开(公告)号：US20050269641A1
公开(公告)日：2005-12-08
申请号：US10904475
申请日：2004-11-12
申请人： Chun-Hsiang Lai , Shin Su , Chia-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
发明人： Chun-Hsiang Lai , Shin Su , Chia-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
IPC分类号： H01L23/60 , H01L27/02 , H01L29/72 , H01L29/74
CPC分类号： H01L27/0266 , H01L29/7436 , H01L29/87
摘要： An electrostatic discharge (ESD) protection circuit coupled to an input pad comprises a diode formed in a substrate and coupled to the input pad; a P deep well formed in the substrate; an N well formed in the P deep well; a first P+ doped region in the N well; and an NMOS transistor formed on the substrate, comprising a gate, a source and a drain, wherein the drain is formed in the N well and coupled to a Vcc, and the source is formed in the P deep well; and a second P+ doped region formed in the P deep well. The ESD protection circuit uses a smaller area than the conventional ESD protection circuit.
摘要翻译：耦合到输入焊盘的静电放电（ESD）保护电路包括形成在衬底中并耦合到输入焊盘的二极管; 在衬底中形成的P阱; 在P深井中形成N井; N阱中的第一P +掺杂区; 以及形成在所述衬底上的NMOS晶体管，包括栅极，源极和漏极，其中所述漏极形成在所述N阱中并且耦合到Vcc，并且所述源极形成在所述P阱中; 以及形成在P深井中的第二P +掺杂区域。 ESD保护电路使用比常规ESD保护电路更小的面积。

17. 发明申请

US20050133868A1 [ELECTRO-STATIC DISCHARGE PROTECTION CIRCUIT FOR DUAL-POLARITY INPUT/OUTPUT PAD] 有权
标题翻译： [双极输入/输出板电静电放电保护电路]
公开(公告)号：US20050133868A1
公开(公告)日：2005-06-23
申请号：US10708171
申请日：2004-02-12
申请人： Shin Su , Chun-Hsiang Lai , Chia-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
发明人： Shin Su , Chun-Hsiang Lai , Chia-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
IPC分类号： H01L23/60 , H01L23/62 , H01L27/02 , H01L29/74
CPC分类号： H01L27/0262 , H01L29/7436
摘要： An electro-static discharge (ESD) protection circuit for a dual polarity I/O pad is provided. The protection circuit includes a substrate of first type; a deep well region of second type disposed in the first type substrate; a well region of first type disposed in the second type deep well region; a first transistor disposed over the well region of first type, wherein the first transistor has a first source, a first gate and a first drain; a second transistor disposed over the substrate of first type, wherein the second transistor has a second source, a second gate and a second drain, and the second source is connected with the first drain, and both of them are disposed in a portion of the well region of first type, the deep well region of second type and the substrate of first type; a first doped region is disposed in the first type well region and laterally adjacent to the first source; a second doped region is disposed in the substrate of first type and laterally adjacent to the second drain.
摘要翻译：提供用于双极性I / O焊盘的静电放电（ESD）保护电路。保护电路包括第一类型的衬底; 设置在所述第一类型基板中的第二类型的深阱区域; 设置在第二类型深井区域中的第一类型井区域; 第一晶体管设置在第一类型的阱区上，其中第一晶体管具有第一源极，第一栅极和第一漏极; 设置在第一类型的衬底上的第二晶体管，其中第二晶体管具有第二源极，第二栅极和第二漏极，并且第二源极与第一漏极连接，并且它们都被布置在第一类井区，第二类深井区和第一类的基底; 第一掺杂区域设置在第一类型阱区域中并且横向邻近于第一源极; 第二掺杂区域设置在第一类型的衬底中并且横向邻近于第二漏极。

18. 发明申请

US20050047036A1 ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad 有权
标题翻译： ESD保护结构和方法利用高耐压焊盘的基板触发
公开(公告)号：US20050047036A1
公开(公告)日：2005-03-03
申请号：US10854792
申请日：2004-05-27
申请人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Yen-Hung Yeh , Chia-Ling Lu , Tao-Cheng Lu
发明人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Yen-Hung Yeh , Chia-Ling Lu , Tao-Cheng Lu
IPC分类号： H01L23/60 , H01L27/02 , H02H9/00
CPC分类号： H01L27/0266
摘要： In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.
摘要翻译：在ESD保护结构和方法中，利用衬底触发用于衬底上的高耐压焊盘，ESD保护器件具有连接到焊盘的源极和连接到地的栅极和漏极，以及衬底触发控制电路用于在正常操作期间将衬底保持在低电压，并且在ESD事件期间将衬底泵送到高电压以使ESD保护器件被触发得更容易。基板触发控制电路由有源器件实现，从而减小电路的芯片尺寸和对焊盘的负载效应。

19. 发明授权

US07291870B2 Electrostatic protection circuit 有权
标题翻译：静电保护电路
公开(公告)号：US07291870B2
公开(公告)日：2007-11-06
申请号：US10904475
申请日：2004-11-12
申请人： Chun-Hsiang Lai , Shin Su , Chia-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
发明人： Chun-Hsiang Lai , Shin Su , Chia-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
IPC分类号： H01L29/72
CPC分类号： H01L27/0266 , H01L29/7436 , H01L29/87
摘要： An electrostatic discharge (ESD) protection circuit coupled to an input pad comprises a diode formed in a substrate and coupled to the input pad; a P deep well formed in the substrate; an N well formed in the P deep well; a first P+ doped region in the N well; and an NMOS transistor formed on the substrate, comprising a gate, a source and a drain, wherein the drain is formed in the N well and coupled to a Vcc, and the source is formed in the P deep well; and a second P+ doped region formed in the P deep well. The ESD protection circuit uses a smaller area than the conventional ESD protection circuit.
摘要翻译：耦合到输入焊盘的静电放电（ESD）保护电路包括形成在衬底中并耦合到输入焊盘的二极管; 在衬底中形成的P阱; 在P深井中形成N井; N阱中的第一P +掺杂区; 以及形成在所述衬底上的NMOS晶体管，包括栅极，源极和漏极，其中所述漏极形成在所述N阱中并耦合到Vcc，并且所述源极形成在所述P阱中; 以及形成在P深井中的第二P +掺杂区域。 ESD保护电路使用比常规ESD保护电路更小的面积。

20. 发明授权

US07187527B2 Electrostatic discharge conduction device and mixed power integrated circuits using same 有权
标题翻译：静电放电传导器件和混合功率集成电路使用相同
公开(公告)号：US07187527B2
公开(公告)日：2007-03-06
申请号：US10933181
申请日：2004-09-02
申请人： Shin Su , Chun-Hsiang Lai , Cha-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
发明人： Shin Su , Chun-Hsiang Lai , Cha-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
IPC分类号： H02H9/00
CPC分类号： H01L27/0251 , H01L27/0292
摘要： A device for connection between supply buses in mixed power integrated circuits includes a diode in series with a transistor with an active p-ring in a semiconductor substrate. The active p-ring surrounds the source and drain of the transistor with a conductive region having the same conductivity type as the semiconductor substrate. A control circuit coupled to the p-ring applies a bias voltage in response to an ESD event affecting the first and second conductors. The bias voltage tends to inject carriers into the semiconductor substrate which enables discharge of the short voltage pulse via a parasitic SCR in the substrate from the anode of the diode to the source of the transistor.
摘要翻译：用于在混合功率集成电路中的电源总线之间连接的装置包括与在半导体衬底中具有有源p型环的晶体管串联的二极管。有源P环围绕具有与半导体衬底相同的导电类型的导电区域的晶体管的源极和漏极。耦合到p型环的控制电路响应于影响第一和第二导体的ESD事件施加偏置电压。偏置电压倾向于将载流子注入到半导体衬底中，其能够通过衬底中的寄生SCR从二极管的阳极到晶体管的源极放电短电压脉冲。

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