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11. 发明申请

US20060256616A1 Semiconductor device that enables simultaneous read and write/read operation 有权
标题翻译：实现同时读/写操作的半导体器件
公开(公告)号：US20060256616A1
公开(公告)日：2006-11-16
申请号：US11453830
申请日：2006-06-16
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C16/04
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device includes a memory cell array including a plurality of cores, each of said cores including one block or a plurality of blocks. The semiconductor device further includes a first power supply line which is provided commonly for said plurality of cores and which provides a data reading power supply potential; a second power supply line which is provided commonly for said plurality of cores and which provides a data writing or erasing power supple potential; and a power supply line switching circuit which is provided for each of said plurality of cores and which selectively connects a corresponding one of said plurality of cores to said first power supply line or said second power supply line in accordance with whether said corresponding one of said plurality of cores is in a data read mode or a data write or erase mode.
摘要翻译：半导体器件包括包括多个核的存储单元阵列，每个所述核包括一个块或多个块。所述半导体器件还包括第一电源线，所述第一电源线通常为所述多个芯提供，并提供数据读取电源电位; 第二电源线，其为所述多个核心共同提供，并且提供数据写入或擦除功率补偿电位; 以及电源线切换电路，其被设置用于所述多个芯中的每一个，并且根据所述多个核中的所述相应一个选择性地将所述多个核中的相应一个核连接到所述第一电源线或所述第二电源线多个核心处于数据读取模式或数据写入或擦除模式。

12. 发明申请

US20060227619A1 Nonvolatile semiconductor memory device which stores multivalue data 有权
标题翻译：存储多值数据的非易失性半导体存储器件
公开(公告)号：US20060227619A1
公开(公告)日：2006-10-12
申请号：US11401286
申请日：2006-04-11
申请人： Yasuhiko Honda , Masao Kuriyama
发明人： Yasuhiko Honda , Masao Kuriyama
IPC分类号： G11C11/34
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5634
摘要： A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.
摘要翻译：参考电流产生电路产生至少一个参考电流。电压产生电路产生电压。感测放大器根据从电压产生电路提供的电压与从参考电流产生电路提供的参考电流将存储单元中的流量引起的电流进行比较。控制部分被提供有读出放大器的输出信号。当验证存储单元的阈值电压时，控制部分使得电压产生电路产生与从存储器单元读出数据时产生的读出电压相同的验证电压。

13. 发明申请

US20070236998A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH STORES MULTIVALUE DATA 有权
标题翻译：存储数据数据的非易失性半导体存储器件
公开(公告)号：US20070236998A1
公开(公告)日：2007-10-11
申请号：US11763690
申请日：2007-06-15
申请人： Yasuhiko Honda , Masao Kuriyama
发明人： Yasuhiko Honda , Masao Kuriyama
IPC分类号： G11C16/28
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5634
摘要： A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.
摘要翻译：参考电流产生电路产生至少一个参考电流。电压产生电路产生电压。感测放大器根据从电压产生电路提供的电压与从参考电流产生电路提供的参考电流将存储单元中的流量引起的电流进行比较。控制部分被提供有读出放大器的输出信号。当验证存储单元的阈值电压时，控制部分使得电压产生电路产生与从存储器单元读出数据时产生的读出电压相同的验证电压。

14. 发明授权

US07126855B2 Semiconductor device that enables simultaneous read and write/read operation 失效
标题翻译：实现同时读/写操作的半导体器件
公开(公告)号：US07126855B2
公开(公告)日：2006-10-24
申请号：US11125073
申请日：2005-05-10
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.
摘要翻译：半导体器件具有存储单元阵列，其具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义作为数据擦除单位的存储单元的范围。半导体器件具有存储体设置存储器电路，其被配置为选择核心的可选数量的核心作为第一存储体，并且将剩余的核心设置为第二存储体，以便允许数据读取操作以在第一和第二组中的另一个中进行数据写入或擦除操作的第一和第二存储体。

15. 发明申请

US20050207247A1 Semiconductor device that enables simultaneous read and write/read operation 失效
公开(公告)号：US20050207247A1
公开(公告)日：2005-09-22
申请号：US11125073
申请日：2005-05-10
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C16/00 , G11C5/00 , G11C8/12 , G11C16/10 , G11C16/26
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.

16. 发明授权

US06920057B2 Semiconductor device that enables simultaneous read and write/read operation 有权
标题翻译：实现同时读/写操作的半导体器件
公开(公告)号：US06920057B2
公开(公告)日：2005-07-19
申请号：US10860275
申请日：2004-06-04
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C16/00 , G11C5/00 , G11C8/12 , G11C16/10 , G11C16/26 , G11C5/02
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.
摘要翻译：半导体器件具有存储单元阵列，其具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义作为数据擦除单位的存储单元的范围。半导体器件具有存储体设置存储器电路，其被配置为选择核心的可选数量的核心作为第一存储体，并且将剩余的核心设置为第二存储体，以便允许数据读取操作以在第一和第二组中的另一个中进行数据写入或擦除操作的第一和第二存储体。

17. 发明授权

US06717852B2 Nonvolatile semiconductor memory device capable of concurrently and reliably writing/erasing and reading memory cores 有权
标题翻译：能够同时且可靠地写入/擦除和读取存储器核的非易失性半导体存储器件
公开(公告)号：US06717852B2
公开(公告)日：2004-04-06
申请号：US10267693
申请日：2002-10-10
申请人： Yasuhiko Honda , Hideo Kato , Masao Kuriyama , Hidetoshi Saito , Tokumasa Hara
发明人： Yasuhiko Honda , Hideo Kato , Masao Kuriyama , Hidetoshi Saito , Tokumasa Hara
IPC分类号： G11C1632
CPC分类号： G11C16/08 , G11C7/1042 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor memory device, which allows concurrent execution of a write/erase operation and a read operation, is provided for each core with a core busy output circuit which has a function of, at the start, end, suspending or resuming of a write/erase operation, setting the sequence in which a command to write into/erase or read from a core, a core select signal indicating whether or not the core has been selected, and a busy signal indicating that the core is in the write/erase mode are set or reset so that multiple selection of a core in a write/erase operation and a core in a read operation does not occur.
摘要翻译：为每个核心提供一个允许并行执行写入/擦除操作和读取操作的半导体存储器件，其具有核心忙输出电路，其具有在开始和结束时挂起或恢复写/ 擦除操作，设置写入/擦除或从内核读取的命令的顺序，指示核心是否被选择的核心选择信号以及指示核心处于写/擦除模式的忙信号被设置或复位，使得在写入/擦除操作中的核心和读取操作中的核心不会发生多次选择。

18. 发明授权

US06320800B1 Semiconductor memory and nonvolatile semiconductor memory having redundant circuitry for replacing defective memory cell 有权
标题翻译：具有用于替换有缺陷的存储单元的冗余电路的半导体存储器和非易失性半导体存储器
公开(公告)号：US06320800B1
公开(公告)日：2001-11-20
申请号：US09583540
申请日：2000-06-01
申请人： Hidetoshi Saito , Masao Kuriyama , Yasuhiko Honda , Hideo Kato
发明人： Hidetoshi Saito , Masao Kuriyama , Yasuhiko Honda , Hideo Kato
IPC分类号： G11C700
CPC分类号： G11C29/78 , G11C8/06 , G11C16/26 , G11C2216/22
摘要： Redundant cell arrays 201 of a plurality of columns are provided for replacing a defective bit line of a memory cell array 101. Each of the redundant cell arrays 201 is provided with a redundant sense amplifier circuit 105 separately from a sense amplifier circuit 103 of the memory cell array 101. A defective address storing circuit 108 stores a defective address of the memory cell array 101, an input/output terminal, to and from which data corresponding to the defective address are. to be inputted and outputted, and a column set number of the redundant cell array which is to be replaced in accordance with the input/output terminal. An address comparator circuit 109 detects the coincidence of an input address with the defective address. A switch circuit 112 is controlled by the coincidence detection output to switch one corresponding to the defective address of a sense amplifier circuit to one selected by the set number in the redundant sense amplifier circuit, to connect it to a data input/output buffer 113. Thus, it is possible to provide a semiconductor memory capable of effectively relieving a plurality of defective columns and a defect in a boundary region in column directions of the cell array.
摘要翻译：多个列的冗余单元阵列201被提供用于替换存储单元阵列101的有缺陷的位线。每个冗余单元阵列201设置有与存储器的读出放大器电路103分离的冗余读出放大器电路105 单元阵列101.缺陷地址存储电路108存储与缺陷地址对应的数据的存储单元阵列101的缺陷地址，输入/输出端。输入和输出，以及根据输入/输出端子要替换的冗余单元阵列的列组号。地址比较电路109检测输入地址与缺陷地址的一致性。开关电路112由重合检测输出控制，将与读出放大器电路的缺陷地址对应的一个切换到由冗余读出放大器电路中的设定数字选择的一个，将其连接到数据输入/输出缓冲器113。因此，可以提供能够有效地消除多个缺陷列的半导体存储器和单元阵列的列方向上的边界区域中的缺陷。

19. 发明申请

US20070296487A1 Voltage generation circuit and method thereof 有权
标题翻译：电压产生电路及其方法
公开(公告)号：US20070296487A1
公开(公告)日：2007-12-27
申请号：US11812682
申请日：2007-06-21
申请人： Masao Kuriyama
发明人： Masao Kuriyama
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F3/262
摘要： A voltage generation circuit may include a static current circuit and/or a current mirror. The static current circuit may include a first resistor. The current mirror may include a second resistor, a third resistor, and/or an output terminal.
摘要翻译：电压产生电路可以包括静态电流电路和/或电流镜。静态电流电路可以包括第一电阻器。电流镜可以包括第二电阻器，第三电阻器和/或输出端子。

20. 发明授权

US07120053B2 Semiconductor intergrated circuit device with a main cell array and a fuse cell array whose word lines and bit lines are extended in the same directions 失效
标题翻译：半导体集成电路器件具有主单元阵列和熔丝单元阵列，其字线和位线在相同方向上延伸
公开(公告)号：US07120053B2
公开(公告)日：2006-10-10
申请号：US11033398
申请日：2005-01-12
申请人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
发明人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
IPC分类号： G11C16/22
CPC分类号： G11C5/143 , G11C5/14 , G11C7/1045 , G11C16/26 , G11C16/30
摘要： A semiconductor integrated circuit device includes a main cell array, a fuse cell array, main cell word lines arranged at the main cell array, and fuse cell word lines arranged at the fuse cell array. The fuse cell word lines are formed in a same direction as a direction of the main cell word lines.
摘要翻译：半导体集成电路器件包括主单元阵列，熔丝单元阵列，布置在主单元阵列处的主单元字线以及布置在熔丝单元阵列处的熔丝单元字线。熔丝单元字线形成在与主单元字线的方向相同的方向上。

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