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11. 发明申请

US20060132206A1 Trimming method and apparatus for voltage controlled delay loop with central interpolator 有权
标题翻译：具有中央插补器的电压控制延迟环微调方法和装置
公开(公告)号：US20060132206A1
公开(公告)日：2006-06-22
申请号：US11020022
申请日：2004-12-22
申请人： Ronald Freyman , Mohammad Mobin , Vladimir Sindalovsky , Lane Smith
发明人： Ronald Freyman , Mohammad Mobin , Vladimir Sindalovsky , Lane Smith
IPC分类号： H03L7/00
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/0818
摘要： Methods and apparatus are provided for trimming a desired delay element in a voltage controlled delay loop. The disclosed trimming process comprises the steps of obtaining a first phase signal of a reference clock; applying the first phase signal along a first path to the desired delay element and a common delay element connected in series to the desired delay element; applying the reference clock along a second path to a first delay element and the common delay element; measuring a delay difference between the first and second paths at an output of the common delay element; and adjusting a delay of the desired delay element based on the measured delay difference. The trimming method may be repeated for each delay element in a voltage controlled delay loop.
摘要翻译：提供了用于在电压控制的延迟环中修整期望的延迟元件的方法和装置。所公开的修剪过程包括获得参考时钟的第一相位信号的步骤; 将第一相位信号沿着第一路径施加到期望的延迟元件和与期望的延迟元件串联连接的公共延迟元件; 沿着第二路径将参考时钟施加到第一延迟元件和公共延迟元件; 测量所述公共延迟元件的输出处的所述第一和第二路径之间的延迟差; 以及基于所测量的延迟差来调整所述延迟元件的延迟。可以在电压控制的延迟环路中对每个延迟元件重复修整方法。

12. 发明申请

US20120257693A1 CDR WITH SIGMA-DELTA NOISE-SHAPED CONTROL 有权
标题翻译： CDR与SIGMA-DELTA噪声控制
公开(公告)号：US20120257693A1
公开(公告)日：2012-10-11
申请号：US13081941
申请日：2011-04-07
申请人： Vladimir Sindalovsky , Lane Smith , Shawn Logan
发明人： Vladimir Sindalovsky , Lane Smith , Shawn Logan
IPC分类号： H04L27/06
CPC分类号： H04L7/033 , H03L7/101 , H04L7/0004 , H04L25/03057
摘要： In described embodiments, a receiver includes a clock and data recovery (CDR) module with a voltage control oscillator (VCO) and a Sigma-Delta modulator in an integral loop control of the VCO. Providing finer resolution by the Sigma-Delta modulator reduces quantization noise in the integral control loop when compared to a loop without a Sigma-Delta modulator in the integral loop. Sigma-Delta modulation within the integral loop control of a VCO-based CDR reduces effective quantization of the VCO integral word control, allowing the proportional loop control compensation to i) reduce effective quantization of the VCO integral word control and, ii) enhance receiver jitter tolerance in presence of periodic-jitter, serial data whose frequency is offset from the nominal rate and serial data whose nominal frequency is modulated by a spread spectrum clock.
摘要翻译：在所描述的实施例中，接收机包括具有VCO的积分环路控制中的压控振荡器（VCO）和Σ-Δ调制器的时钟和数据恢复（CDR）模块。当与积分环路中没有Σ-Δ调制器的环路相比时，通过Sigma-Delta调制器提供更精细的分辨率降低了积分控制环路中的量化噪声。在基于VCO的CDR的积分环路控制中的Σ-Δ调制降低了VCO积分字控制的有效量化，允许比例环路控制补偿以减少VCO积分字控制的有效量化，以及ii）增强接收器抖动存在频率偏离标称速率的串行数据的周期抖动的容限以及标称频率由扩频时钟调制的串行数据。

13. 发明申请

US20070052460A1 Statically controlled clock source generator for VCDL clock phase trimming 失效
公开(公告)号：US20070052460A1
公开(公告)日：2007-03-08
申请号：US11221316
申请日：2005-09-07
申请人： Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , Lane Smith , Craig Ziemer
发明人： Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , Lane Smith , Craig Ziemer
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , H04L7/0337
摘要： The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations in these output clocks. The invention's use of a controlled clock source eliminates the need for this trimming process to be conducted in real time and reduces the expense of the circuitry required.

14. 发明申请

US20060268958A1 Methods and apparatus for spread spectrum generation using a voltage controlled delay loop 有权
标题翻译：使用电压控制延迟环路进行扩频生成的方法和装置
公开(公告)号：US20060268958A1
公开(公告)日：2006-11-30
申请号：US11141695
申请日：2005-05-31
申请人： Vladimir Sindalovsky , Lane Smith , Craig Ziemer
发明人： Vladimir Sindalovsky , Lane Smith , Craig Ziemer
IPC分类号： H04B1/00
CPC分类号： H04B15/02 , H04B2215/067
摘要： Methods and apparatus are provided for generating a frequency with a predefined offset from a reference frequency. A spread spectrum generator circuit is disclosed that comprises a voltage controlled delay loop for generating a plurality of signals having a different phase; and at least one interpolator for processing at least two of the signals to generate an output signal having a phase between a phase of the at least two of the signals, wherein the output is varied between a phase of the at least two of the signals to generate the spread spectrum. A spread spectrum having a frequency lower than an applied clock signal is generated using a continuous phase delay increase and a spread spectrum having a frequency higher than the clock signal is generated using a continuous phase delay decrease.
摘要翻译：提供了用于产生具有与参考频率的预定义偏移的频率的方法和装置。公开了一种扩频发生器电路，其包括用于产生具有不同相位的多个信号的电压控制延迟环路; 以及至少一个内插器，用于处理至少两个所述信号以产生具有所述至少两个所述信号的相位之间的相位的输出信号，其中所述输出在所述至少两个信号的相位之间变化生成扩频。使用连续的相位延迟增加来产生频率低于所施加的时钟信号的扩展频谱，并且使用连续的相位延迟减小产生具有高于时钟信号的频率的扩频。

15. 发明申请

US20060267635A1 Multiple phase detection for delay loops 有权
标题翻译：延迟环路的多相检测
公开(公告)号：US20060267635A1
公开(公告)日：2006-11-30
申请号：US11138703
申请日：2005-05-26
申请人： Peter Metz , Vladimir Sindalovsky , Lane Smith
发明人： Peter Metz , Vladimir Sindalovsky , Lane Smith
IPC分类号： G01R29/00
CPC分类号： H03L7/07 , H03L7/087 , H03L7/097 , H03L7/0998 , H04L7/033
摘要： A circuit (e.g., a receiver) has a delay loop (e.g., a voltage-controlled delay loop) and (at least) two phase detectors (PDs), where each PD compares a different pair of clock signals generated by the delay loop. The outputs of the different PDs are then used to generate a control signal for adjusting the delays provided by the delay elements in the delay loop. In one implementation, the control signal indicates that a delay adjustment should be made only if both PDs agree on that adjustment. This multiple-PD technique can reduce jitter that could otherwise result from a non-50% duty cycle in the reference clock signal used by the delay loop to generate its multiple clock signals.
摘要翻译：电路（例如，接收器）具有延迟环路（例如，电压控制的延迟环路）和至少两个相位检测器（PD），其中每个PD比较由延迟环路产生的不同的时钟信号对。然后使用不同PD的输出来产生用于调整由延迟环路中的延迟元件提供的延迟的控制信号。在一个实现中，控制信号指示仅当两个PD同意该调整时才应进行延迟调整。这种多PD技术可以减少由延迟环使用的参考时钟信号中的非50％占空比产生其多个时钟信号的抖动。

16. 发明授权

US08494092B2 CDR with sigma-delta noise-shaped control 有权
标题翻译： CDR具有Σ-Δ噪声形控制
公开(公告)号：US08494092B2
公开(公告)日：2013-07-23
申请号：US13081941
申请日：2011-04-07
申请人： Vladimir Sindalovsky , Lane Smith , Shawn Logan
发明人： Vladimir Sindalovsky , Lane Smith , Shawn Logan
IPC分类号： H04L27/00
CPC分类号： H04L7/033 , H03L7/101 , H04L7/0004 , H04L25/03057
摘要： In described embodiments, a receiver includes a clock and data recovery (CDR) module with a voltage control oscillator (VCO) and a Sigma-Delta modulator in an integral loop control of the VCO. Providing finer resolution by the Sigma-Delta modulator reduces quantization noise in the integral control loop when compared to a loop without a Sigma-Delta modulator in the integral loop. Sigma-Delta modulation within the integral loop control of a VCO-based CDR reduces effective quantization of the VCO integral word control, allowing the proportional loop control compensation to i) reduce effective quantization of the VCO integral word control and, ii) enhance receiver jitter tolerance in presence of periodic-jitter, serial data whose frequency is offset from the nominal rate and serial data whose nominal frequency is modulated by a spread spectrum clock.
摘要翻译：在所描述的实施例中，接收机包括具有VCO的积分环路控制中的压控振荡器（VCO）和Σ-Δ调制器的时钟和数据恢复（CDR）模块。当与积分环路中没有Σ-Δ调制器的环路相比时，通过Sigma-Delta调制器提供更精细的分辨率降低了积分控制环路中的量化噪声。在基于VCO的CDR的积分环路控制中的Σ-Δ调制降低了VCO积分字控制的有效量化，允许比例环路控制补偿以减少VCO积分字控制的有效量化，以及ii）增强接收器抖动存在频率偏离标称速率的串行数据的周期抖动的容限以及标称频率由扩频时钟调制的串行数据。

17. 发明申请

US20070002992A1 Method and apparatus for automatic clock alignment 有权
标题翻译：自动时钟对准的方法和装置
公开(公告)号：US20070002992A1
公开(公告)日：2007-01-04
申请号：US11174228
申请日：2005-07-01
申请人： Vladimir Sindalovsky , Lane Smith
发明人： Vladimir Sindalovsky , Lane Smith
IPC分类号： H03D3/24
CPC分类号： H03L7/07 , H03L7/0814 , H04L7/0337
摘要： The present invention synchronizes signals generated and used in different clock domains. The invention is applicable to a CDR circuit in which phase adjustment of a multiphase clock to the phase of incoming data is implemented by controlling phase offsets from the PLL frequency relative to data sampling points Si and transition sampling points Ti. In particular, these offsets are controlled by both coarse and fine adjustments. Typically CDR circuits employ feedback phase control information being supplied to the VCDL. The above described adjustments result in these phase control signals having an arbitrary and time-changing relation to the PLL clock. By properly selecting an appropriate edge of the PLL clock signal, the present invention synchronizes these phase control signals into the PLL clock domain in order to apply VCDL control in a synchronous manner.
摘要翻译：本发明使在不同时钟域中产生和使用的信号同步。本发明可应用于CDR电路，其中通过从相对于数据采样点S 1和N 2的转换采样点控制来自PLL频率的相位偏移来实现多相时钟到输入数据相位的相位调整 T 。特别地，这些偏移由粗调和微调两者来控制。通常，CDR电路使用提供给VCDL的反馈相位控制信息。上述调整导致这些相位控制信号具有与PLL时钟的任意和时变关系。通过适当地选择PLL时钟信号的适当边沿，本发明将这些相位控制信号同步到PLL时钟域中，以便以同步方式应用VCDL控制。

18. 发明申请

US20060176943A1 Serializer deserializer (SERDES) testing 有权
公开(公告)号：US20060176943A1
公开(公告)日：2006-08-10
申请号：US11051801
申请日：2005-02-04
申请人： Vladimir Sindalovsky , Lane Smith
发明人： Vladimir Sindalovsky , Lane Smith
IPC分类号： H04B17/00
CPC分类号： G01R31/31716
摘要： The various embodiments of the invention provide an apparatus, system and method of testing a serializer and deserializer data communication apparatus (SERDES). The serializer and deserializer data communication apparatus has a plurality of serialize data communication channels adapted to convert parallel data to serial data and a plurality of deserialize data communication channels adapted to convert serial data to parallel data. An exemplary method provides for coupling an output of a serialize data communication channel and an input of a deserialize data communication channel to provide a serial data loop-back connection and coupling an output of a deserialize data communication channel and an input of a serialize data communication channel to provide a parallel data loop-back connection. Input test data is provided to a first serialize or deserialize data communication channel, and is successively serialized and deserialized through each corresponding serialize data communication channel and deserialize data communication channel to provide output test data. The output test data and the input test data are then compared, with SERDES devices having acceptable or unacceptable bit error rates respectively designated as passed or failed.

19. 发明申请

US20060114039A1 Voltage controlled delay loop and method with injection point control 有权
标题翻译：电压控制延时回路和注入点控制方法
公开(公告)号：US20060114039A1
公开(公告)日：2006-06-01
申请号：US10999900
申请日：2004-11-30
申请人： Ronald Freyman , Vladimir Sindalovsky , Lane Smith
发明人： Ronald Freyman , Vladimir Sindalovsky , Lane Smith
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/0814 , H03L7/087 , H04L7/0337
摘要： A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises a plurality of delay elements; and an input that selectively injects a reference clock into any one of the plurality of delay elements. The plurality of delay elements are connected in series, such as in a loop. In one exemplary implementation, each delay element has an associated multiplexer that selects one of the reference clock and a signal from a previous delay element.
摘要翻译：公开了用于时钟和数据恢复应用的电压控制延迟环路和方法。电压控制延迟环路产生具有相似频率和不同相位的时钟信号。电压控制延迟环包括多个延迟元件; 以及输入，其选择性地将参考时钟注入到所述多个延迟元件中的任一个中。多个延迟元件串联连接，例如循环。在一个示例性实现中，每个延迟元件具有相关联的多路复用器，其选择参考时钟之一和来自先前延迟元件的信号。

20. 发明申请

US20050289496A1 Symmetric signal distribution through abutment connection 失效
标题翻译：通过对接连接的对称信号分配
公开(公告)号：US20050289496A1
公开(公告)日：2005-12-29
申请号：US10880216
申请日：2004-06-29
申请人： Jung Cho , Robert Kylor , Vladimir Sindalovsky , Lane Smith
发明人： Jung Cho , Robert Kylor , Vladimir Sindalovsky , Lane Smith
IPC分类号： G06F17/50 , H03K19/00
CPC分类号： G06F17/5072 , G06F17/5077
摘要： The present invention provides a method and apparatus for managing a large number of associated interconnects within an integrated circuit involving a modular approach to the macro cell layout. In particular, internal signal paths are created within each macro cell that permit connections to other macros by abutting these macros adjacent to one another. Moreover, these internal signal paths permit efficient distribution of a common source signal to each of such connected macros. The layout of the internal macro cell signal paths of the present invention also permits each of these macros to be reflected about its Y-axis, thereby increasing its versatility in being utilized in various circuit designs.
摘要翻译：本发明提供一种用于管理涉及宏小区布局的模块化方法的集成电路内的大量相关互连的方法和装置。特别地，在每个宏小区内创建内部信号路径，允许通过将这些宏邻接的方式连接到其他宏。此外，这些内部信号路径允许将公共源信号有效地分配给每个这样连接的宏。本发明的内部宏单元信号路径的布局还允许这些宏中的每一个都围绕其Y轴反射，从而增加其在各种电路设计中的使用的多功能性。

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